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| ZL50417 Unmanaged 16-Port 10/100M + 2-Port 1G Ethernet Switch Data Sheet Features * * ntegrated Single-Chip 10/100/1000 Mbps Ethernet Switch 16 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS). Each port can independently use one of the two interfaces. 2 Gigabit Ports with GMII, PCS, 10/100 options per port Serial CPU interface for configuration Supports two Frame Buffer Memory domains with SRAM at 100 MHz Supports memory size 2 MB, or 4 MB Applies centralized shared memory architecture Up to 64K MAC addresses Maximum throughput is 3.6 Gbps non-blocking High performance packet forwarding (10.712M packets per second) at full wire speed Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Supports Ethernet multicasting and broadcasting and flooding control Supports per-system option to enable flow control for best effort frames even on QoSenabled ports Traffic Classification Ordering Information ZL50417/GKC 553 PIN HSBGA February 2003 -40C to +85C * 4 transmission priorities for Fast Ethernet ports with 2 dropping levels * Classification based on: - Port based priority - VLAN Priority field in VLAN tagged frame - DS/TOS field in IP packet - UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range * The precedence of the above classifications is programmable. QoS Support * Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and WFQ service disciplines * Provides 2 levels of dropping precedence with WRED mechanism * * * * * * * * * * * * * * VLAN I MCT Frame Data Buffer A SRAM (1M/ 2M) VLAN I MCT Frame Data Buffer B SRAM (1M/ 2M) FDB Interface LED MCT Link FCB Frame Engine Search Engine 16 x 10/100 RMII Ports 0-15 GMII/ PCS Port 0 GMII/ PCS Port 1 Management Module Figure 1 - System Block Diagram 1 ZL50417 Data Sheet * * * * * * * * * * User controls the WRED thresholds. * Buffer management: per class and per port buffer reservations * Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID. 3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100 ports per group. Or 8 groups for 10/100 ports with up to 2 10/100 ports per group Load sharing among trunked ports can be based on source MAC and/or destination MAC. The Gigabit trunking group has one more option, based on source port. Port Mirroring to a dedicated mirroring port Full set of LED signals provided by a serial interface, or 6 LED signals dedicated to Gigabit port status only (without serial interface) Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports Built-in reset logic triggered by system malfunction Built-In Self Test for internal and external SRAM IC EEPROM for configuration 553 BGA package Description The ZL50417 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps, 2 ports at 1000 Mbps. The Gigabit ports can also support 10/100M. The chip supports up to 64K MAC addresses. The centralized shared memory architecture permits a very high performance packet forwarding rate at up to 5.357M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously. With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the ZL50417 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, and UDP/TCP logical port fields in IP packets. The ZL50417 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50417 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports, and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50417 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to SERDES chips. The PCS can be bypassed to provide a GMII interface. The ZL50417 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The ZL50417 is packaged in a 553-pin Ball Grid Array package. 2 Zarlink Semiconductor Inc. Data Sheet Table of Contents ZL50417 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.1 Frame Data Buffer (FDB) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.2 GMII/PCS MAC Module (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3 Physical Coding Sublayer (PCS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.4 10/100 MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.5 Configuration Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.6 Frame Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.7 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.8 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.9 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1 Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 IC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.2 Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.0 ZL50417 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.2 Detailed Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3 Memory Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.0 Search Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.3.1 MAC Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.3.3 Aging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.4 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.5 Priority Classification Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5.6 Port-Based VLAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.7 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 6.2 Frame Engine Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.2.1 FCB Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.2.3 RxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.3 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.4 TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Zarlink Semiconductor Inc. 3 ZL50417 Table of Contents Data Sheet 7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 Four QoS Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 Delay Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 Strict Priority and Best Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6 Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.8 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.8.1 Dropping When Buffers Are Scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.9 ZL50417 Flow Control Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.9.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.9.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.10 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.4 Trunking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.0 Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Port Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 Setting Registers for Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.0 TBI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.1 TBI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.0 GPSI (7WS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 GPSI connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2 SCAN LINK and SCAN COL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1 LED Interface Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.2 Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.3 LED Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.1 ZL50417 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.2 (Group 0 Address) MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2.1 ECR1Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2.2 ECR2Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.3 GGControl - Extra GIGA Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.3 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3.1 AVTCL - VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3.2 AVTCH - VLAN Type Code Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3.3 PVMAP00_0 - Port 00 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3.4 PVMAP00_1 - Port 00 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3.5 PVMAP00_3 - Port 00 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4 Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4.1 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.5 (Group 2 Address) Port Trunking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.5.1 TRUNK0_MODE- Trunk group 0 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.5.2 TRUNK1_MODE - Trunk group 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.5.3 TRUNK2_MODE - Trunk group 2 mode (Gigabit ports 1 and 2). . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.5.4 RQSS - Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.6 (Group 4 Address) Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 Zarlink Semiconductor Inc. Data Sheet Table of Contents ZL50417 13.6.1 AGETIME_LOW - MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 13.6.2 AGETIME_HIGH -MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 13.6.3 SE_OPMODE - Search Engine Operation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 13.7 (Group 5 Address) Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 13.7.1 FCBAT - FCB Aging Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 13.7.2 QOSC - QOS Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 13.7.3 FCR - Flooding Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 13.7.4 AVPML - VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 13.7.5 AVPMM - VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 13.7.6 AVPMH - VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 13.7.7 TOSPML - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 13.7.8 TOSPMM - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 13.7.9 TOSPMH - TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 13.7.10 AVDM - VLAN Discard Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 13.7.11 TOSDML - TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 13.7.12 BMRC - Broadcast/Multicast Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 13.7.13 UCC - Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 13.7.14 MCC - Multicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 13.7.15 PR100 - Port Reservation for 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 13.7.16 PRG - Port Reservation for Giga ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 13.7.17 SFCB - Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 13.7.18 C2RS - Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 13.7.19 C3RS - Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 13.7.20 C4RS - Class 4 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 13.7.21 C5RS - Class 5 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 13.7.22 C6RS - Class 6 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 13.7.23 C7RS - Class 7 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 13.7.24 QOSCn - Classes Byte Limit Set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 13.7.25 Classes Byte Limit Set 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 13.7.26 Classes Byte Limit Set 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 13.7.27 Classes Byte Limit Set 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 13.7.28 Classes Byte Limit Giga Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 13.7.29 Classes Byte Limit Giga Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 13.7.30 Classes WFQ Credit Set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 13.7.31 Classes WFQ Credit Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 13.7.32 Classes WFQ Credit Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 13.7.33 Classes WFQ Credit Set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 13.7.34 Classes WFQ Credit Port G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 13.7.35 Classes WFQ Credit Port G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 13.7.36 Class 6 Shaper Control Port G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 13.7.37 Class 6 Shaper Control Port G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 13.7.38 RDRC0 - WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 13.7.39 RDRC1 - WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 13.7.40 User Defined Logical Ports and Well Known Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 13.7.40.1 USER_PORT0_(0~7) - User Define Logical Port (0~7) . . . . . . . . . . . . . . . . . . . . . . . . . . .70 13.7.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority . . . . . . . . . . . . .70 13.7.40.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority . . . . . . . . . . . . .71 13.7.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . . . . . . . . . .71 13.7.40.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority . . . . . . . . . . . . .71 13.7.40.6 USER_PORT_ENABLE[7:0] - User Define Logic 7 to 0 Port Enables. . . . . . . . . . . . . . . .71 13.7.40.7 WELL_KNOWN_PORT[1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . .72 13.7.40.8 WELL_KNOWN_PORT[3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . .72 Zarlink Semiconductor Inc. 5 ZL50417 Table of Contents Data Sheet 13.7.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 72 13.7.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . 72 13.7.40.11 WELL KNOWN_PORT_ENABLE [7:0] - Well Known Logic 7 to 0 Port Enables. . . . . . . 73 13.7.40.12 RLOWL - User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.7.40.13 1RLOWH - User Define Range Low Bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.7.40.14 RHIGHL - User Define Range High Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.7.40.15 RHIGHH - User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.7.40.16 RPRIORITY - User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.8 (Group 6 Address) MISC Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.8.1 MII_OP0 - MII Register Option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.8.2 MII_OP1 - MII Register Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.8.3 FEN - Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.8.4 MIIC0 - MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.8.5 MIIC1 - MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.8.6 MIIC2 - MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13.8.7 MIIC3 - MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13.8.8 MIID0 - MII Data Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13.8.9 MIID1 - MII Data Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13.8.10 LED Mode - LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.8.11 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.9 (Group 7 Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.9.1 MIRROR1_SRC - Port Mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.9.2 MIRROR1_DEST - Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.9.3 MIRROR2_SRC - Port Mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.9.4 MIRROR2_DEST - Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.10 (Group F Address) CPU Access Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.10.1 GCR-Global Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.10.2 DCR-Device Status and Signature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.10.3 DCR1-Giga port status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.10.4 DPST - Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.10.5 DTST - Data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.10.6 PLLCR - PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.10.7 LCLK - LA_CLK delay from internal OE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.10.8 OECLK - Internal OE_CLK delay from SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.10.9 DA - DA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.11 TBI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.11.1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.11.2 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.11.3 Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.11.4 Link Partner Ability Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.11.5 Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.11.6 Extended Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.1 BGA Views (TOP-View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.2 Power and Ground Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.2.1 Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.3 Ball Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.4 AC/DC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.4.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.4.3 Recommended Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.5 Local Frame Buffer SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6 Zarlink Semiconductor Inc. Data Sheet Table of Contents ZL50417 14.5.1 Local SBRAM Memory Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 14.6 Local Switch Database SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 14.6.1 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 14.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 14.7.1 Reduced Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 14.7.2 Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 14.7.3 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 14.7.4 SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 14.7.5 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 14.7.6 IC Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 14.7.7 Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Zarlink Semiconductor Inc. 7 ZL50417 Data Sheet 8 Zarlink Semiconductor Inc. Data Sheet List of Tables ZL50417 Table 1 - Supported Memory Configurations (Pipeline SBRAM Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 2 - Options for Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 3 - Two-dimensional World Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4 - Four QoS Configurations for a 10/100 Mbps Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5 - Four QoS Configurations for a Gigabit Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6 - Mapping between ZL50417 and IETF Diffserv Classes for Gigabit Ports . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 7 - Mapping between ZL50417 and IETF Diffserv Classes for 10/100 Ports . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 8 - ZL50417 Features Enabling IETF Diffserv Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 9 - Select via trunk0_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10 - Select via trunk1_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 11 - Individually Enabled/disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 12 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 13 - Input Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 14 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 15 - Input Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 16 - SCANLINK, SCANCOL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 17 - MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 18 - IC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 19 - Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Zarlink Semiconductor Inc. 9 ZL50417 Data Sheet 10 Zarlink Semiconductor Inc. Data Sheet List of Figures ZL50417 Figure 1 - System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Data Transfer Format for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3 - Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4 - Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5 - ZL50417 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6 - Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7 - Priority Classification Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8 - Memory Configuration For: 2 banks, 1 Layer, 2MB total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9 - Memory Configuration For: 2 banks, 2 Layers, 4MB total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10 - Memory Configuration For: 2 banks, 1 Layer, 4MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11 - Summary of the Behaviour of the WRED Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 12 - Buffer Partition Scheme Used to Implement Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 13 - TBI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 14 - GPSI (7WS) mode connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 15 - SCAN LINK and SCAN COLLISON status diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 16 - Timing Diagram of LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 17 - Local Memory Interface - Input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 18 - Local Memory Interface - Output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 19 - Local Memory Interface - Input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 20 - Local Memory Interface - Output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 21 - AC Characteristics - Reduced media independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 22 - AC Characteristics - Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 23 - AC Characteristics- GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 24 - AC Characteristics - Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 25 - Gigabit TBI Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 26 - Gigabit TBI Interface Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 27 - AC Characteristics- GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 28 - AC Characteristics - Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 29 - Gigabit TBI Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 30 - Gigabit TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 31 - AC Characteristics - LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 32 - SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 33 - SCANLINK, SCANCOL Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 34 - MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 35 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 36 - IC Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 37 - IC Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 38 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 39 - Serial Interface Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Zarlink Semiconductor Inc. 11 ZL50417 Data Sheet 12 Zarlink Semiconductor Inc. Data Sheet 1.0 1.1 ZL50417 Block Functionality Frame Data Buffer (FDB) Interfaces The FDB interface supports pipelined synchronous burst SRAM (SBRAM) memory at 100 MHz. To ensure a nonblocking switch, two memory domains are required. Each domain has a 64 bit wide memory bus. At 100 MHz, the aggregate memory bandwidth is 12.8 Gbps, which is enough to support 16 10/100 Mbps and 2 Gigabit ports at full wire speed switching. The Switching Database is also located in the external SRAM; it is used for storing MAC addresses and their physical port number. It is duplicated and stored in both memory domains. Therefore, when the system updates the contents of the switching database, it has to write the entry to both domains at the same time. 1.2 GMII/PCS MAC Module (GMAC) The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The ZL50417 GMAC implements both GMII and MII interface, which offers a simple migration from 10/100 to 1G. The GMAC of the ZL50417 meets the IEEE 802.3Z specification. It is able to operate in 10M/100M either Half or Full Duplex mode with a back pressure/flow control mechanism or in 1G Full duplex mode with flow control mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. PHY addresses for GMAC are 01h and 02h. For fiber optics media, the ZL50417 implements the Physical Code Sublayer (PCS) interface. The PCS includes an 8B10B encoder and decoder, auto-negotiation, and Ten Bit Interface (TBI). 1.3 Physical Coding Sublayer (PCS) Interface For the ZL50417, the 1000BASE-X PCS Interface is designed internally and may be utilized in the absence of a GMII. The PCS incorporates all the functions required by the GMII to include encoding (decoding) 8B GMII data to (from) 8B/10B TBI format for PHY communication and generating Collision Detect (COL) signals for half-duplex mode. It also manages the Auto negotiation process by informing the management entity that the PHY is ready for communications. The on-chip TBI may be disabled if TBI exists within the Gigabit PHY. The TBI interface provides a uniform interface for all 1000 Mbps PHY implementations. The PCS comprises the PCS Transmit, Synchronization, PCS Receive, and Auto negotiation processes for 1000BASE-X. The PCS Transmit process sends the TBI signals TXD [9:0] to the physical medium and generates the GMII Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission. Additionally, the Transmit process generates an internal "transmitting" flag and monitors Auto negotiation to determine whether to transmit data or to reconfigure the link. The PCS Synchronization process determines whether or not the receive channel is operational. The PCS Receive process generates RXD [7:0] on the GMII from the TBI data [9:0], and the internal "receiving" flag for use by the Transmit processes. The PCS Auto negotiation process allows the ZL50417 to exchange configuration information between two devices that share a link segment, and to automatically configure the link for the appropriate speed of operation for both devices. Zarlink Semiconductor Inc. 13 ZL50417 1.4 10/100 MAC Module (RMAC) Data Sheet The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The ZL50417 has two interfaces, RMII or Serial (only for 10M). The 10/100 MAC of the ZL50417 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. The PHY addresses for 16 10/100 MAC are from 08h to 1Fh. 1.5 Configuration Interface Module Once The ZL50417 supports a serial and an I2C interface, which provides an easy way to configure the system. configured, the resulting configuration can be stored in an I2C EEPROM. 1.6 Frame Engine The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent to the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent. 1.7 Search Engine The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2) or IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority assignment, and trunking functions. 1.8 LED Interface The LED interface provides a serial interface for carrying 16+2 port status signals. It can also provide direct status pins (6) for the two Gigabit ports. 1.9 Internal Memory Several internal tables are required and are described as follows: * * Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame stored in the FDB, e.g. frame size, read/write pointer, transmission priority, etc. MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. The external MAC table is located in the FDB Memory. Note that the external MAC table is located in the external SSRAM Memory. 2.0 2.1 System Configuration Configuration Mode The ZL50417 can be configured by EEPROM (24C02 or compatible) via an IC interface at boot time, or via a synchronous serial interface during operation. 14 Zarlink Semiconductor Inc. Data Sheet 2.2 IC Interface ZL50417 The IC interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure 2 depicts the data transfer format. START SLAVE ADDRESS R/W ACK DATA 1 (8 bits) ACK DATA2 ACK DATAM ACK STOP Figure 2 - Data Transfer Format for I2C Interface 2.2.1 Start Condition Generated by the master (in our case, the ZL50417). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the IC bus is free, both lines are High. 2.2.2 Address The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address. 2.2.3 Data Direction The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R. 2.2.4 Acknowledgment Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition. 2.2.5 Data After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB first. 2.2.6 Stop Condition Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line. The IC interface serves the function of configuring the ZL50417 at boot time. The master is the ZL50417, and the slave is the EEPROM memory. Zarlink Semiconductor Inc. 15 ZL50417 2.3 Synchronous Serial Interface Data Sheet The synchronous serial interface serves the function of configuring the ZL50417 not at boot time but via a PC. The PC serves as master and the ZL50417 serves as slave. The protocol for the synchronous serial interface is nearly identical to the IC protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. The unmanaged ZL50417 uses a synchronous serial interface to program the internal registers. To reduce the number of signals required, the register address, command and data are shifted in serially through the D0 pin. STROBE- pin is used as the shift clock. AUTOFD- pin is used as data return path. Each command consists of four parts. * * * * START pulse Register Address Read or Write command Data to be written or read back Any command can be aborted in the middle by sending a ABORT pulse to the ZL50417. A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when STROBE- fall. An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when STROBE- fall. 2.3.1 Write Command STROBE2 Extra clocks after last transfer D0 A0 START A1 A2 ... A9 A10 A11 W D0 D1 D2 D3 D4 D5 D6 D7 DATA ADDRESS COMMAND Figure 3 - Write Command 2.3.2 Read Command STROBE- D0 A0 START A1 A2 ... A9 A10 A11 R DATA ADDRESS COMMAND AUTOFD- D0 D1 D2 D3 D4 D5 D6 D7 Figure 4 - Read Command 16 Zarlink Semiconductor Inc. Data Sheet All registers in ZL50417 can be modified through this synchronous serial interface. ZL50417 3.0 3.1 ZL50417 Data Forwarding Protocol Unicast Data Frame Forwarding When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. The memory (SRAM) interface is two 64-bit buses, connected to two SRAM banks, A and B. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn," the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests. The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-portper-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 4 transmission classes for each of the 16 10/ 100 ports, and 8 classes for each of the two Gigabit ports - a total of 112 unicast queues. The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line. 3.2 Multicast Data Frame Forwarding After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 2 multicast queues for each of the 16 10/100 ports. The queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entries. There are 4 multicast queues for each of the two Gigabit ports. The size of the queues are: 32 entries (higher priority queue), 32 entries, 32 entries and 64 entries (lower priority queue). There is one multicast queue for every two priority classes. For the 10/100 ports to map the 8 Zarlink Semiconductor Inc. 17 ZL50417 Data Sheet transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the gigabit ports to map the 8 transmit priorities into 4 multicast queues, the LSB are discarded. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined. 4.0 4.1 Memory Interface Overview The ZL50417 provides two 64-bit-wide SRAM banks, SRAM Bank A and SRAM Bank B, with a 64-bit bus connected to each. Each DMA can read and write from both bank A and bank B. The following figure provides an overview of the ZL50417 SRAM banks. SRAM Bank A SRAM Bank B TXDMA 0-7 TXDMA 8-15 RXDMA 0-7 RXDMA 8-15 Figure 5 - ZL50417 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) 4.2 Detailed Memory Information Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B, and so on in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then from B, and so on. The reading and writing from alternating memory banks can be performed with minimal waste of memory bandwidth. What's the worst case? For any speed port, in the worst case, a 1-byte-long EOF granule gets written to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next 8-byte segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A, not B. This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the interframe gap is 20 bytes. 18 Zarlink Semiconductor Inc. Data Sheet 4.3 Memory Requirements ZL50417 To speed up searching and decrease memory latency, the external MAC address database is duplicated in both memory banks. To support 64K MAC address, 4 MB memory is required. When VLAN support is enabled, 512 entries of the MAC address table are used for storing the VLAN ID at VLAN Index Mapping Table. Up to 2K Ethernet frame buffers are supported and they will use 3 MB of memory. Each frame uses 1536 bytes. The maximum system memory requirement is 4 MB. If less memory is desired, the configuration can scale down. Memory Configuration Bank A 1M 1M 2M 2M 1M 1M 2M 2M Bank B Tag based VLAN Disable Enable Disable Enable Frame Buffer 1K 1K 2K 2K Max MAC Address 32K 31.5K 64K 63.5K Memory Map 1M Bank A 0.75M 0.25M 1M Bank B 0.75M 0.25M 2M Bank A 1.5M 0.5M 2M Bank B 1.5M 0.5M Tag based VLAN Disable 1M Bank A 0.75M 0.25M - 4K 1M Bank B 0.75M 0.25M2M Bank A 1.5M 0.5M - 4K 4K 2M Bank B 1.5M 0.5M 4K 4K 4K Tag based VLAN Enable Frame Data Buffer (FDR) Area MAC Address Control Table (MCT) Area VLAN Table Area Figure 6 - Memory Map Zarlink Semiconductor Inc. 19 ZL50417 5.0 5.1 Data Sheet Search Engine Search Engine Overview The ZL50417 search engine is optimized for high throughput searching, with enhanced features to support: * * * * * * * * * Up to 64K MAC addresses Up to 255 VLAN and IP Multicast groups 3 groups of port trunking (1 for the two Gigabit ports, and 2 others) Traffic classification into 4 (or 8 for Gigabit) transmission priorities, and 2 drop precedence levels Packet filtering Security IP Multicast Flooding, Broadcast, Multicast Storm Control MAC address learning and aging 5.2 Basic Flow Shortly after a frame enters the ZL50417 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, the transmission and discard priorities, whether the frame is unicast or multicast, and VLAN ID. Requests are sent to the external SRAM to locate the associated entries in the external hash table. When all the information has been collected from external SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). In addition, port based VLAN information is used to select the correct set of destination ports for the frame (for multicast), or to verify that the frame's destination port is associated with the VLAN (for unicast). If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. When all the information is compiled, the switch response is generated, as stated earlier. 5.3 5.3.1 Search, Learning, and Aging MAC Search The search block performs source MAC address and destination MAC address searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. 20 Zarlink Semiconductor Inc. Data Sheet ZL50417 In port based VLAN mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing port. When the egress port is not included in the ingress port VLAN bitmap, the packet is discarded. The MAC search block is also responsible for updating the source MAC address timestamp and the VLAN port association timestamp, used for aging. 5.3.2 Learning The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. 5.3.3 Aging Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table. 5.4 Quality of Service Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate traffic, a service level known as "best effort" attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. In a congested network or when a low-performance switch/router is overloaded, "best effort" becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously plagued such "best effort" networking systems. QoS provides Ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth. Extensive core QoS mechanisms are built into the ZL50417 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue(WFQ) scheduling at the egress port. In the ZL50417, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. For example, the overall service given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay. The ZL50417 supports the following QoS techniques: In a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority. In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be mapped to different queues in the switch to provide QoS. In a TOS/DS-based set up, TOS stands for "Type of Service" that may include "minimize delay," "maximize throughput," or "maximize reliability." Network nodes may select routing paths or forwarding behaviors that are suitably engineered to satisfy the service request. Zarlink Semiconductor Inc. 21 ZL50417 Data Sheet In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as VoIP. 5.5 Priority Classification Rule Figure 7 shows the ZL50417 priority classification rule. Figure 7 - Priority Classification Rule 22 Zarlink Semiconductor Inc. Data Sheet 5.6 Port-Based VLAN ZL50417 An administrator can use the PVMAP Registers to configure the ZL50417 for port-based VLAN (see "Registration Definition" on page 42). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50417 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50417 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. Gigabit port 0 and 1 are denoted as Port 25 and 26 respectively. Destination Port Numbers Bit Map Port Registers Register for Port #0 PVMAP00_0[7:0] to PVMAP00_3[2:0] Register for Port #1 PVMAP01_0[7:0] to PVMAP01_3[2:0] Register for Port #2 PVMAP02_0[7:0] to PVMAP02_3[2:0] ... Register for Port #18 PVMAP26_0[7:0] to PVMAP26_3[2:0] 0 0 0 0 18 0 0 0 ... 2 1 1 0 1 1 0 0 0 0 1 0 For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. In this example: Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2. Data packets received at port #2 are NOT eligible to be sent to ports 0 and 1. Zarlink Semiconductor Inc. 23 ZL50417 5.7 Memory Configurations Data Sheet The ZL50417 supports the following memory configurations. Pipeline SBRAM modes support 1 M and 2M per bank configurations. For detail connection information, please reference the memory application note. 1 M per bank (Bootstrap pin TSTOUT7 = open) Two 128 K x 32 SRAM/bank or One 128 K x 64 SRAM/bank Configuration 2 M per bank (Bootstrap pin TSTOUT7 = pull down) Two 256K x 32 SRAM/bank Connections Single Layer (Bootstrap pin TSTOUT13 = open) Double Layer (Bootstrap pin TSTOUT13 = pull down) Connect 0E# and WE# NA Four 128 K x 32 SRAM/bank or Two 128 K x 64 SRAM/bank Connect 0E0# and WE0# Connect 0E1# and WE1# Table 1 - Supported Memory Configurations (Pipeline SBRAM Mode) Only Bank A 1M (SRAM) ZL50415 ZL50416 ZL50417 ZL50418 X X X X X X 2M (SRAM) Bank A and Bank B 1M/bank (SRAM) 2M/bank (SRAM) X X Table 2 - Options for Memory Configuration 24 Zarlink Semiconductor Inc. Data Sheet BANK A (1M One Layer) Data LA_D[63:32] ZL50417 BANK B (1M One Layer) Data LB_D[63:32] Data LA_D[31:0] SRAM Memory 128 K 32 bits Data LB_D[31:0] Memory 128 K 32 bits SRAM Memory 128 K 32 bits Memory 128 K 32 bits Address LA_A[19:3] Address LB_A[19:3] Bootstraps: TSTOUT7 = Open, TSTOUT13 = Open, TSTOUT4 = Open Figure 8 - Memory Configuration For: 2 banks, 1 Layer, 2MB total BANK A (2M Two Layers) Data LA_D[63:32] BANK B (2M Two Layers) Data LB_D[63:32] Data LA_D[31:0] SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits Data LB_D[31:0] SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits Address LA_A[19:3] Address LB_A[19:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open Figure 9 - Memory Configuration For: 2 banks, 2 Layers, 4MB total Zarlink Semiconductor Inc. 25 ZL50417 Data Sheet BANK A (2M One Layer) Data LA_D[63:32] BANK B (2M One Layer) Data LB_D[63:32] Data LA_D[31:0] SRAM Memory 256 K 32 bits Data LB_D[31:0] Memory 256 K 32 bits SRAM Memory 256 K 32 bits Memory 256 K 32 bits Address LA_A[20:3] Address LB_A[20:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open Figure 10 - Memory Configuration For: 2 banks, 1 Layer, 4MB Total 6.0 6.1 Frame Engine Data Forwarding Summary When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface. A switch request is sent to the Search Engine. The Search Engine processes the switch request. A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast, and its destination port or ports. A VLAN table lookup is performed as well. A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are 4 TxSch Q for each 10/100 port (and 8 per Gigabit port), one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older HOL between the two queues goes first. For 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. For Gigabit ports multicast queue 0 is associated with unicast queue 0, multicast queue 1 with unicast queue 2, multicast queue 2 with unicast queue 4 and multicast queue 3 with unicast queue 6. The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 26 Zarlink Semiconductor Inc. Data Sheet 6.2 Frame Engine Details ZL50417 This section briefly describes the functions of each of the modules of the ZL50417 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be determined by referring to Chapter 7. In addition, the FCB manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register FCBAT. 6.2.2 Rx Interface The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch request. 6.2.3 RxDMA The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 TxQ Manager First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the TxQ manager requests that the FCB manager link the unicast frame's FCB to the correct per-port-per-class TxQ. If multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port control module. 6.3 Port Control The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released. 6.4 TxDMA The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. Zarlink Semiconductor Inc. 27 ZL50417 7.0 7.1 Data Sheet Quality of Service and Flow Control Model Quality of service is an all-encompassing term for which different people have different interpretations. In general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch's performance. Table 6 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. Gigabit ports actually have eight total transmission priorities. Goals Total Assured Bandwidth (user defined) 50 Mbps Low Drop Probability (low-drop) High Drop Probability (high-drop) Apps: training video. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to drop otherwise. Apps: non-critical interactive apps. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed; firstP2 to drop otherwise. Apps: casual web browsing. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed; first to drop otherwise. Highest transmission priority, P3 Apps: phone calls, circuit emulation. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed. Apps: interactive apps, Web business. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed. Apps: emails, file backups. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed. Middle transmission priority, P2 37.5 Mbps Low transmission priority, P1 12.5 Mbps Total 100 Mbps Table 3 - Two-dimensional World Traffic A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreedupon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the quality of service (QoS) received by well-behaved classes. As Table 6 illustrates, the six traffic types may each have their own distinct properties and applications. As shown, classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 Mbps of bandwidth at that port. 28 Zarlink Semiconductor Inc. Data Sheet ZL50417 Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50417, each 10/100 Mbps port will support four total classes, and each 1000 Mbps port will support eight classes. We will discuss the various modes of scheduling these classes in the next section. In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely lose packets. But poorly behaved users - users who send frames at too high a rate - will encounter frame loss, and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. Table 6 shows that different types of applications may be placed in different boxes in the traffic table. For example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category of low-loss, low-latency traffic. 7.2 Four QoS Configurations There are four basic pieces to QoS scheduling in the ZL50417: strict priority (SP), delay bound, weighted fair queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as shown in the tables below. For 10/100 Mbps ports, the following registers select these modes: QOSC24 [7:6]_CREDIT_C00 QOSC28 [7:6]_CREDIT_C10 QOSC32 [7:6]_CREDIT_C20 QOSC36 [7:6]_CREDIT_C30 P3 Op1 (default) Op2 Op3 Op4 Delay Bound SP SP WFQ P2 P1 BE P0 Delay Bound WFQ BE Table 4 - Four QoS Configurations for a 10/100 Mbps Port QOSC40 [7:6] and QOSC48 [7:6] select these modes for the first and second gigabit ports, respectively. P7 Op1 (default) Op2 Op3 Op4 Delay Bound SP SP WFQ P6 P5 P4 P3 P2 P1 BE P0 Delay Bound WFQ BE Table 5 - Four QoS Configurations for a Gigabit Port Zarlink Semiconductor Inc. 29 ZL50417 Data Sheet The default configuration for a 10/100 Mbps port is three delay-bounded queues and one best-effort queue. The delay bounds per class are 0.8 ms for P3, 3.2 ms for P2, and 12.8 ms for P1. For a 1 Gbps port, we have a default of six delay-bounded queues and two best-effort queues. The delay bounds for a 1 Gbps port are 0.16 ms for P7 and P6, 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. Best effort traffic is only served when there is no delay-bounded traffic to be served. For a 1 Gbps port, where there are two best-effort queues, P1 has strict priority over P0. We have a second configuration for a 10/100 Mbps port in which there is one strict priority queue, two delay bounded queues, and one best effort queue. The delay bounds per class are 3.2 ms for P2 and 12.8 ms for P1. If the user is to choose this configuration, it is important that P3 (SP) traffic be either policed or implicitly bounded (e.g. if the incoming P3 traffic is very light and predictably patterned). Strict priority traffic, if not admission-controlled at a prior stage to the ZL50417, can have an adverse effect on all other classes' performance. For a 1 Gbps port, P7 and P6 are both SP classes, and P7 has strict priority over P6. In this case, the delay bounds per class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. The third configuration for a 10/100 Mbps port contains one strict priority queue and three queues receiving a bandwidth partition via WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled. In the fourth configuration, all queues are served using a WFQ service discipline. 7.3 Delay Bound In the absence of a sophisticated QoS server and signaling protocol, the ZL50417 may not know the mix of incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL) frames. As a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. Our algorithm also differentiates between high-drop and low-drop traffic with a weighted random early drop (WRED) approach. Random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip's buffers are completely full, while still largely sparing lowdrop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. Finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 7.4 Strict Priority and Best Effort When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes. When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance. However, in a typical network setting, much best effort traffic will indeed be transmitted, and with an adequate degree of expediency. Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the ZL50417, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best effort and strict priority queues when global buffer resources become scarce. 30 Zarlink Semiconductor Inc. Data Sheet 7.5 Weighted Fair Queuing ZL50417 In some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, WFQ may be preferable to a delay-bounded scheduling discipline. The ZL50417 provides the user with a WFQ option with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. The user sets four WFQ "weights" (eight for Gigabit ports) such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with error within 2%. In WFQ mode, though we do not assure frame latency, the ZL50417 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do indeed drop frames from SP queues for global buffer management purposes. In addition, queue P0 for a 10/100 port (and queues P0 and P1 for a Gigabit port) are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 Shaper Although traffic shaping is not a primary function of the ZL50417, the chip does implement a shaper for expedited forwarding (EF). Our goal in shaping is to control the peak and average rate of traffic exiting the ZL50417. Shaping is limited to the two Gigabit ports only, and only to class P6 (the second highest priority). This means that class P6 will be the class used for EF traffic. If shaping is enabled for P6, then P6 traffic must be scheduled using strict priority. With reference to Table 8, only the middle two QoS configurations may be used. Peak rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then the peak rate for shaped traffic is 32/64 * 1000 Mbps = 500 Mbps. Average rate is also a programmable whole number, no greater than 64, and no greater than the peak rate. For example, if the setting is 16, then the average rate for shaped traffic is 16/64 * 1000 Mbps = 250 Mbps. As a consequence of the above settings in our example, shaped traffic will exit the ZL50417 at a rate always less than 500 Mbps, and averaging no greater than 250 Mbps. See Programming QoS Register application note for more information. Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. Though we do have global resource management, we do nothing to prevent this situation locally. We assume SP traffic is policed at a prior stage to the ZL50417. 7.7 WRED Drop Threshold Management Support To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic. Figure 11 - Summary of the Behaviour of the WRED Logic Zarlink Semiconductor Inc. 31 ZL50417 Data Sheet Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds for each priority queue. They can be programmed by the QOS control register (refer to the register group 5). See Programming QoS Registers application note for more information. 7.8 Buffer Management Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the ZL50417. Our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in Figure 12 on page 33. As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the ZL50417, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100 Mbps ports, a frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only four transmission scheduling queues for 10/100 Mbps ports, but as far as buffer usage is concerned, there are still eight distinguishable classes. Another segment of the FDB reserves space for each of the 18 ports. Two parameters can be set, one for the source port reservation for 10/100 Mbps ports, and one for the source port reservation for 1 Gbps ports. These 18 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port. The following registers define the size of each section of the Frame data Buffer: PR100- Port Reservation for 10/100 Ports PRG- Port Reservation for Giga Ports SFCB- Share FCB Size C2RS- Class 2 Reserve Size C3RS- Class 3 Reserve Size C4RS- Class 4 Reserve Size C5RS- Class 5 Reserve Size C6RS- Class 6 Reserve Size C7RS- Class 7 Reserve Size 32 Zarlink Semiconductor Inc. Data Sheet ZL50417 Figure 12 - Buffer Partition Scheme Used to Implement Buffer Management 7.8.1 Dropping When Buffers Are Scarce Summarizing the two examples of local dropping discussed earlier in this chapter: If a queue is a delay-bounded queue, we have a multilevel WRED drop scheme, designed to control delay and partition bandwidth in case of congestion. If a queue is a WFQ-scheduled queue, we have a multilevel WRED drop scheme, designed to prevent congestion. In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer management is to make sure that such dropping causes as little blocking as possible. 7.9 ZL50417 Flow Control Basics Because frame loss is unacceptable for some applications, the ZL50417 provides a flow control option. When flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch, to temporarily hold off. While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. A single packet destined for a congested output can block other packets destined for uncongested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. Zarlink Semiconductor Inc. 33 ZL50417 Data Sheet In the ZL50417, each source port can independently have flow control enabled or disabled. For flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priority. What this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible expense of minimum bandwidth or maximum delay assurances. In addition, these "downgraded" frames may only use the shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not use reserved FDB slots for the highest six classes (P2-P7). The ZL50417 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for frames originating from flow control enabled ports. When this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. The reason is that intelligent packet dropping is a major component of the ZL50417's approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.9.1 Unicast Flow Control For unicast frames, flow control is triggered by source port resource availability. Recall that the ZL50417's buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is triggered when a port is currently being flow controlled, and all of that port's reserved FDB slots have been released. Note that the ZL50417's per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.9.2 Multicast Flow Control In unmanaged mode, flow control for multicast frames is triggered by a global buffer counter. When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold. In addition, each source port has a 18-bit port map recording which port or ports of the multicast frame's fanout were congested at the time Xoff was triggered. All ports are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were originally marked as congested in the port map have become uncongested, then Xon is triggered, and the 18-bit vector is reset to zero. 7.10 Mapping to IETF Diffserv Classes The mapping between priority classes discussed in this chapter and elsewhere is shown below. ZL504xx IETF P7 NM P6 EF P5 AF0 P4 AF1 P3 AF2 P2 AF3 P1 BE0 P0 BE1 Table 6 - Mapping between ZL50417 and IETF Diffserv Classes for Gigabit Ports As the table illustrates, P7 is used solely for network management (NM) frames. P6 is used for expedited forwarding service (EF). Classes P2 through P5 correspond to an assured forwarding (AF) group of size 4. Finally, P0 and P1 are two best effort (BE) classes. 34 Zarlink Semiconductor Inc. Data Sheet ZL50417 For 10/100 Mbps ports, the classes of Table 7 are merged in pairs--one class corresponding to NM+EF, two AF classes, and a single BE class. ZL504xx IETF P3 NM+EF P2 AF0 P1 AF1 P0 BE0 Table 7 - Mapping between ZL50417 and IETF Diffserv Classes for 10/100 Ports Features of the ZL50417 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) Global buffer reservation for NM and EF Shaper for EF traffic on 1 Gbps ports Option of strict priority scheduling No dropping if admission controlled Four AF classes for 1 Gbps ports Programmable bandwidth partition, with option of WFQ service Option of delay-bounded service keeps delay under fixed levels even if not admissioncontrolled Random early discard, with programmable levels Global buffer reservation for each AF class Two BE classes for 1 Gbps ports Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE Assured forwarding (AF) Best effort (BE) Table 8 - ZL50417 Features Enabling IETF Diffserv Standards 8.0 8.1 Port Trunking Features and Restrictions A port group (i.e. trunk) can include up to 4 physical ports, but when using stack all of the ports in a group must be in the same ZL50417. The two Gigabit ports may also be trunked together. There are three trunk groups total, including the option to trunk Gigabit ports. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address. Three other options include source MAC address only, destination MAC address only, and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly. Zarlink Semiconductor Inc. 35 ZL50417 Data Sheet The ZL50417 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the ZL50417 will automatically redistribute the traffic over to the remaining ports in the trunk. 8.2 Unicast Packet Forwarding The search engine finds the destination MCT entry, and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address belongs to a trunk, then the source port's trunk membership register is checked. A hash key, based on some combination of the source and destination MAC addresses for the current packet, selects the appropriate forwarding port, as specified in the Trunk_Hash registers. 8.3 Multicast Packet Forwarding For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the VLAN index and hash key. Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. Determining one forwarding port per group. Preventing the multicast packet from looping back to the source trunk. The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. This is because, when we select the primary forwarding port for each group, we do not take the source port into account. To prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet. 8.4 Trunking In this mode, 3 trunk groups are supported. Groups 0 and 1 can trunk up to 4 10/100 ports. Group 2 can trunk 2 Gigabit ports. The supported combinations are shown in the following table. Group 0 Port 0 ! ! ! Port 1 ! ! ! ! ! ! Port 2 Port 3 Table 9 - Select via trunk0_mode register Group 1 Port 4 ! ! Port 5 ! ! Port 6 Port 7 ! ! Table 10 - Select via trunk1_mode register 36 Zarlink Semiconductor Inc. Data Sheet Group 2 Port 25(Giga 0) ! Port 26 (Giga 1) ! ZL50417 Table 11 - Individually Enabled/disabled The trunks are individually enabled/disabled by controlling pin trunk 0,1,2. 9.0 9.1 Port Mirroring Port Mirroring Features The received or transmitted data of any 10/100 port in the ZL50417 chip can be "mirrored" to any other port. We support two such mirrored source-destination pairs. A mirror port can not also serve as a data port. 9.2 Setting Registers for Port Mirroring MIRROR1_SRC: Sets the source port for the first port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR1_DEST: Sets the destination port for the first port mirroring pair. Bits [4:0] select the destination port to be mirrored. MIRROR2_SRC: Sets the source port for the second port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 0. Refer to Port Mirroring Application Notes for further information. Zarlink Semiconductor Inc. 37 ZL50417 10.0 10.1 Data Sheet TBI Interface TBI Connection The TBI interface can be used for 1000Mbps fiber operation. In this mode, the ZL50417 is connected to the Serdes as shown in Figure 13. There are two TBI interfaces in the ZL50417 devices. To enable to TBI function, the corresponding TXEN and TXER pins need to be boot strapped. See Ball - Signal Description for details. M25/26_TXD[9:0] M25/26_TXCLK T[9:0] REFCLK ZL50417 SERDES M25/26_RXD[9:0] M25/26_RXCLK M25/26_COL R[9:0] RBC0 RBC1 Figure 13 - TBI Connection 38 Zarlink Semiconductor Inc. Data Sheet 11.0 11.1 ZL50417 GPSI (7WS) Interface GPSI connection The 10/100 RMII ethernet port can function in GPSI (7WS) mode when the corresponding TXEN pin is strapped low with a 1K pull down resistor. In this mode, the TXD[0], TXD[1], RXD[0] and RXD[1] serve as TX data, TX clock, RX data and RX clock respectively. The link status and collision from the PHY are multiplexed and shifted into the switch device through external glue logic. The duplex of the port can be controlled by programming the ECR register. The GPSI interface can be operated in port based VLAN mode only. CRS_DV RXD[0] RXD[1] TXD[1] TXD[0] TXEN crs rxd rx_clk tx_clk txd txen Port 0 Ethernet PHY link0 col0 link1 col1 5041X link2 col2 Port 15 Ethernet PHY link15 col15 SCAN_LINK SCAN_COL SCAN_CLK Link Serializer (CPLD) Collision Serializer (CPLD) Figure 14 - GPSI (7WS) mode connection diagram Zarlink Semiconductor Inc. 39 ZL50417 11.2 SCAN LINK and SCAN COL interface Data Sheet An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYS and shift them into the switch device. The switch device will drive out a signature to indicate the start of the sequence. After that, the CPLD should shift in the link and collision status of the PHYS as shown in the figure. The extra link status indicates the polarity of the link signal. One indicates the polarity of the link signal is active high. scan_clk scan_link/ scan_col 25 cycles for link/ 24 cycles for col Drived by ZL5041x Drived by CPLD Total 32 cycles period Figure 15 - SCAN LINK and SCAN COLLISON status diagram 12.0 12.1 LED Interface LED Interface Introduction A serial output channel provides port status information from the ZL50417 chips. It requires three additional pins. LED_CLK at 12.5 MHz LED_SYN a sync pulse that defines the boundary between status frames LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time A non-serial interface is also allowed, but in this case, only the Gigabit ports will have status LEDs. A low cost external device (44 pin PAL) is used to decode the serial data and to drive an LED array for display. This device can be customized for different needs. 12.2 Port Status In the ZL50417, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators are: Bit 0: Flow control Bit 1:Transmit data Bit 2: Receive data Bit 3: Activity (where activity includes either transmission or reception of data) Bit 4: Link up Bit 5: Speed (1= 100 Mb/s; 0= 10 Mb/s) 40 Zarlink Semiconductor Inc. Data Sheet Bit 6: Full-duplex Bit 7: Collision ZL50417 Eight clocks are required to cycle through the eight status bits for each port. When the LED_SYN pulse is asserted, the LED interface will present 256 LED clock cycles with the clock cycles providing information for the following ports. Port 0 (10/100): cycles #0 to cycle #7 Port 1 (10/100): cycles#8 to cycle #15 Port 2 (10/100): cycle #16 to cycle #23 ... Port 14 (10/100): cycle #112 to cycle #119 Port 15 (10/100): cycle #120 to cycle #127 Port 25 (Gigabit 1): cycle #192 to cycle #199 Port 26 (Gigabit 2): cycle #200 to cycle #207 Byte 26 (additional status): cycle #208 to cycle #215 Byte 27 (additional status): cycle #216 to cycle #223 Cycles #224 to 256 present data with a value of zero. The first two bits of byte 26 provides the speed information for the Gigabit ports while the remainder of byte 26 and byte 27 provides bist status 26[0]: G0 port (1= port 24 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on speed bit of Port 24) 26[1]: G1 port (1= port 25 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on speed bit of Port 25) 26[2]: initialization done 26[3]: initialization start 26[4]: checksum ok 26[5]: link_init_complete 26[6]: bist_fail 26[7]: ram_error 27[0]: bist_in_process 27[1]: bist_done Zarlink Semiconductor Inc. 41 ZL50417 12.3 LED Interface Timing Diagram Data Sheet The signal from the ZL50417 to the LED decoder is shown in Figure 16. . Figure 16 - Timing Diagram of LED Interface 42 Zarlink Semiconductor Inc. Data Sheet 13.0 13.1 ZL50417 Register Definition ZL50417 Register Description Register Description CPU Addr (Hex) R/W IC Addr (Hex) Default Notes 0. ETHERNET Port Control Registers Substitute [N] with Port number (0..F, 18-1A) ECR1P"N" ECR2P"N" GGC Port Control Register 1 for Port N Port Control Register 2 for Port N Extra GIGA bit control register 0000 + 2 xN 001 + 2 x N 036 R/W R/W R/W 00001A 01B035 NA 020 000 000 1. VLAN Control Registers Substitute [N] with Port number (0..F, 18-1A) AVTCL AVTCH PVMAP"N"_0 PVMAP"N"_1 PVMAP"N"_3 PVMODE PVROUTE7-0 VLAN Type Code Register Low VLAN Type Code Register High Port "N" Configuration Register 0 Port "N" Configuration Register 1 Port "N" Configuration Register 3 VLAN Operating Mode VLAN Router Group Enable 100 101 102 + 4N 103 + 4N 105 + 4N 170 171-178 R/W R/W R/W R/W R/W R/W R/W 036 037 038-052 05306D 0890A3 0A4 NA 000 081 0FF 0FF 007 000 000 2. TRUNK Control Registers TRUNK0_ MODE Trunk Group 0 Mode 203 R/W 0A5 003 3. CPU Port Configuration RQSS TX_AGE Receive Queue Status Transmission Queue Aging Time 324 325 RO R/W NA 0A7 N/A 008 4. Search Engine Configurations AGETIME_LOW AGETIME_ HIGH SE_OPMODE MAC Address Aging Time Low MAC Address Aging Time High Search Engine Operating Mode 400 401 403 R/W R/W R/W 0A8 0A9 NA 2M:05C/ 4M:02E 000 000 5. Buffer Control and QOS Control FCBAT QOSC FCB Aging Timer QOS Control 500 501 R/W R/W 0AA 0AB 0FF 000 Zarlink Semiconductor Inc. 43 ZL50417 CPU Addr (Hex) 502 503 504 505 506 507 508 509 50A 50B 50C 50D 50E 50F 510 511 512 513 514 515 516 517- 51C 51D- 522 523- 52E 52F- 552 553 IC Addr (Hex) 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF 0C0 0C10C6 NA 0C70D2 NA 0FB Data Sheet Register Description R/W Default Notes FCR AVPML AVPMM AVPMH TOSPML TOSPMM TOSPMH AVDM TOSDML BMRC UCC MCC PR100 PRG SFCB C2RS C3RS C4RS C5RS C6RS C7RS QOSC"N" Flooding Control Register VLAN Priority Map Low VLAN Priority Map Middle VLAN Priority Map High TOS Priority Map Low TOS Priority Map Middle TOS Priority Map High VLAN Discard Map TOS Discard Map Broadcast/Multicast Rate Control Unicast Congestion Control Multicast Congestion Control Port Reservation for 10/100 Ports Port Reservation for Giga Ports Share FCB Size Class 2 Reserve Size Class 3 Reserve Size Class 4 Reserve Size Class 5 Reserve Size Class 6 Reserve Size Class 7 Reserve Size QOS Control (N=0 - 5) QOS Control (N=6 - 11) QOS Control (N=12 - 23) QOS Control (N=24 - 59) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 008 000 000 000 000 000 000 000 000 000 2M:008/ 4M:010 050 2M:024/ 4M:036 2M:035/ 4M:058 2M:014/ 4M:064 000 000 000 000 000 000 000 000 000 000 08F RDRC0 WRED Drop Rate Control 0 44 Zarlink Semiconductor Inc. Data Sheet CPU Addr (Hex) 554 580 + 2N 581 + 2N 590 IC Addr (Hex) 0FC 0D60DD 0DE0E5 0E6 ZL50417 Register Description R/W Default Notes RDRC1 USER_ PORT"N"_LOW USER_ PORT"N"_HIGH USER_ PORT1:0_ PRIORITY USER_ PORT3:2_ PRIORITY USER_ PORT5:4_ PRIORITY USER_ PORT7:6_PRI ORITY USER_PORT_ ENABLE WLPP10 WLPP32 WLPP54 WLPP76 WLPE RLOWL RLOWH RHIGHL RHIGHH RPRIORITY WRED Drop Rate Control 1 User Define Logical Port "N" Low (N=0-7) User Define Logical Port "N" High User Define Logic Port 1 and 0 Priority User Define Logic Port 3 and 2 Priority User Define Logic Port 5 and 4 Priority User Define Logic Port 7 and 6 Priority User Define Logic Port Enable Well known Logic Port Priority for 1 and 0 Well known Logic Port Priority for 3 and 2 Well known Logic Port Priority for 5 and 4 Well-known Logic Port Priority for 7 & 6 Well known Logic Port Enable User Define Range Low Bit7:0 User Define Range Low Bit 15:8 User Define Range High Bit 7:0 User Define Range High Bit 15:8 User Define Range Priority R/W R/W R/W R/W 088 000 000 000 591 R/W 0E7 000 592 R/W 0E8 000 593 R/W 0E9 000 594 595 596 597 598 599 59A 59B 59C 59D 59E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0EA 0EB 0EC 0ED 0EE 0EF 0F4 0F5 0D3 0D4 0D5 000 000 000 000 000 000 000 000 000 000 000 6. MISC Configuration Registers MII_OP0 MII_OP1 MII Register Option 0 MII Register Option 1 600 601 R/W R/W 0F0 0F1 000 000 Zarlink Semiconductor Inc. 45 ZL50417 CPU Addr (Hex) 602 603 604 605 606 607 608 609 60B IC Addr (Hex) 0F2 N/A N/A N/A N/A N/A N/A 0F3 0FF Data Sheet Register Description R/W Default Notes FEN MIIC0 MIIC1 MIIC2 MIIC3 MIID0 MIID1 LED SUM Feature Registers MII Command Register 0 MII Command Register 1 MII Command Register 2 MII Command Register 3 MII Data Register 0 MII Data Register 1 LED Control Register EEPROM Checksum Register R/W R/W R/W R/W R/W RO RO R/W R/W 010 000 000 000 000 N/A N/A 000 000 7. Port Mirroring Controls MIRROR1_SRC MIRROR1_ DEST MIRROR2_SRC MIRROR2_ DEST 2 GCR DCR DCR1 DPST DTST DA Global Control Register Device Status and Signature Register Giga Port status Device Port Status Register Data read back register DA Register F00 F01 F02 F03 F04 FFF R/W RO RO R/W RO RO N/A N/A N/A N/A N/A N/A 000 N/A N/A 000 N/A DA Port Mirror 1 Source Port Port Mirror 1 Destination Port Port Mirror 2 Source Port Port Mirror 2 Destination Port 700 701 702 703 R/W R/W R/W R/W N/A N/A N/A N/A 07F 017 0FF 000 46 Zarlink Semiconductor Inc. Data Sheet 13.2 13.2.1 (Group 0 Address) MAC Ports Group ECR1Pn: Port N Control Register ZL50417 IC Address 000 - 01A; CPU Address:0000+2xN (N = port number) Accessed by serial interface and IC (R/W) 7 6 5 A-FC 4 3 2 1 0 Sp State Bit [0] * * * * * Port Mode 1 - Flow Control Off 0 - Flow Control On When Flow Control On: In half duplex mode, the MAC transmitter applies back pressure for flow control. In full duplex mode, the MAC transmitter sends Flow Control frames when necessary. The MAC receiver interprets and processes incoming flow control frames. The Flow Control Frame Received counter is incremented whenever a flow control is received. When Flow Control off: In half duplex mode, the MAC Transmitter does not assert flow control by sending flow control frames or jamming collision. In full duplex mode, the Mac transmitter does not send flow control frames. The MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Received counter is not incremented. 1 - Half Duplex - Only in 10/100 mode 0 - Full Duplex 1 - 10Mbps 0 - 100Mbps 00 - Automatic Enable Auto Neg. - This enables hardware state machine for auto-negotiation. 01 - Limited Disable auto Neg. This disables hardware for speed autonegotiation. Hardware Poll MII for link status. 10 - Link Down. Force link down (disable the port). 11 - Link Up. The configuration in ECR1[2:0] is used for (speed/half duplex/full duplex/flow control) setup. Asymmetric Flow Control Enable. 0 - Disable asymmetric flow control 01 - Enable Asymmetric flow control When this bit is set, and flow control is on (bit[0] = 0), don't send out a flow control frame. But MAC receiver interprets and processes flow control frames. * * * Bit [1] * * Bit [2] * * * * * * Bit [4:3] Bit [5] * * * * Zarlink Semiconductor Inc. 47 ZL50417 Bit [7:6] * * * * * Data Sheet SS - Spanning tree state (802.1D spanning tree protocol) Default is 11. 00 - Blocking: Frame is dropped 01 - Listening: 10 - Learning: Frame is dropped Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. 13.2.2 ECR2Pn: Port N Control Register IC Address: 01B-035; CPU Address:0001+2xN (N = port number) Accessed by serial interface and IC (R/W) 7 6 5 4 3 Reserve 2 DisL 1 Ftf 0 Futf Security En Bit[0]: * * * Bit[1]: * * * Bit[2]: * * * Bit[3]: Bit [5:4:] * * * * QoS Sel Filter untagged frame (Default 0) 0: Disable 1: All untagged frames from this port are discarded or follow security option when security is enable Filter Tag frame (Default 0) 0: Disable 1: All tagged frames from this port are discarded or follow security option when security is enable Learning Disable (Default 0) 1 Learning is disabled on this port 0 Learning is enabled on this port Must be `1' QOS mode selection (Default 00) Determines which of the 4 sets of QoS settings is used for 10/100 ports. Note that there are 4 sets of per-queue byte thresholds, and 4 sets of WFQ ratios programmed. These bits select among the 4 choices for each 10/100 port. Refer to QOS Application Note. 00: select class byte limit set 0 and classes WFQ credit set 0 01: select class byte limit set 1 and classes WFQ credit set 1 10: select class byte limit set 2 and classes WFQ credit set 2 11: select class byte limit set 3 and classes WFQ credit set 3 Security Enable (Default 00). The ZL50417 checks the incoming data for one of the following conditions: If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. * * * * Bit[7:6] * * 48 Zarlink Semiconductor Inc. Data Sheet * ZL50417 A MAC address is defined as secure when its entry at MAC table has static status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted) indicates whether the address is unicast or multicast. As source addresses are always unicast bit 0 is not used (always 0). ZL50417 uses this bit to define secure MAC addresses. If the port is set as learning disable and the source MAC address of the incoming packet is not defined in the MAC address table. If the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. If the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. If one of these three conditions occurs, the packet will be handled according to one of the following specified options: CPU installed - 00 - Disable port security 01 - Discard violating packets 10 - Send packet to CPU and destination port 11 - Send packet to CPU only * * * * * 13.2.3 GGControl - Extra GIGA Port Control CPU Address:h036 Accessed by CPU and serial interface (R/W) 7 DF 6 5 MiiB 4 RstA 3 DF 2 1 MiiA 0 RstA Bit[0]: * Reset GIGA port A 0: Normal operation (default) 1: Reset Gigabit port A. Normally used when a new Phy is connected (Hot swap). Bit[1]: * GIGA port A use MII interface (10/100M) 0: Gigabit port operations at 1000 mode (default) 1: Gigabit port operations at 10/100 mode Bit[2]: Bit[3]: * * Reserved - Must be zero GIGA port A direct flow control (MAC to MAC connection). The ZL50417 supports direct flow control mechanism; the flow control frame is therefore not sent through the Gigabit port data path. - 0: Direct flow control disabled (default) 1: Direct flow control enabled Zarlink Semiconductor Inc. 49 ZL50417 Bit[4]: * Reset GIGA port B - 0: Normal operation (default) Bit[5]: * 1: Reset Gigabit port B Data Sheet GIGA port B use MII interface (10/100M) 0: Gigabit port operates at 1000 mode (default) 1: Gigabit port operates at 10/100 mode Bit[6]: Bit[7]: * * Reserved - Must be zero GIGA port B direct flow control (MAC to MAC connection). ZL50417 supports direct flow control mechanism; the flow control frame is therefore not sent through the Gigabit port data path. - 0: Direct flow control disabled (default) 1: Direct flow control enabled 13.3 13.3.1 (Group 1 Address) VLAN Group AVTCL - VLAN Type Code Register Low IC Address 036; CPU Address:h100 Accessed serial interface and IC (R/W) Bit[7:0]: VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00) 13.3.2 AVTCH - VLAN Type Code Register High IC Address 037; CPU Address:h101 Accessed by serial interface and IC (R/W) Bit[7:0]: VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81) 13.3.3 PVMAP00_0 - Port 00 Configuration Register 0 IC Address 038, CPU Address:h102 Accessed by serial interface and IC (R/W) In Port Based VLAN Mode Bit[7:0]: VLAN Mask for ports 7 to 0 (Default FF) This register indicates the legal egress ports. A "1" on bit 7 means that the packet can be sent to port 7. A "0" on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1, 2 and 3 to form a 27 bit mask to all egress ports. 50 Zarlink Semiconductor Inc. Data Sheet 13.3.4 PVMAP00_1 - Port 00 Configuration Register 1 IC Address h39, CPU Address:h103 Accessed by serial interface and IC (R/W) In Port based VLAN Mode Bit[7:0]: VLAN Mask for ports 15 to 8 (Default is FF) ZL50417 13.3.5 PVMAP00_3 - Port 00 Configuration Register 3 IC Address h3b, CPU Address:h105) Accessed by serial interface and IC (R/W) In Port Based VLAN Mode 7 FP en Bit [2:0]: Bit [5:3]: 6 Drop 5 3 2 0 Default tx priority VLAN Mask VLAN Mask for ports 26 to 24 (Default 7). Default Transmit priority. Used when Bit[7]=1 (Default 0) * 000 Transmit Priority Level 0 (Lowest) * * * * * * * 001 Transmit Priority Level 1 010 Transmit Priority Level 2 011 Transmit Priority Level 3 100 Transmit Priority Level 4 101 Transmit Priority Level 5 110 Transmit Priority Level 6 111 Transmit Priority Level 7 (Highest) Bit [6]: Default Discard priority. Used when Bit[7]=1 (Default 0) * 0 - Discard Priority Level 0 (Lowest) * 1 - Discard Priority Level 1(Highest) Bit [7]: Enable Fix Priority (Default 0) * 0 Disable fix priority. All frames are analyzed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS or Logical Port. * 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3] Zarlink Semiconductor Inc. 51 ZL50417 13.4 Port Configuration Registers Data Sheet PVMAP01_0,1,3 IC Address h3C,3D,3E,3F; CPU Address:h106,107,108,109) PVMAP02_0,1,3 IC Address h40,41,42,43; CPU Address:h10A, 10B, 10C, 10D) PVMAP03_0,1,3 IC Address h44,45,46,47; CPU Address:h10E, 10F, 110, 111) PVMAP04_0,1,3 IC Address h48,49,4A,4B; CPU Address:h112, 113, 114, 115) PVMAP05_0,1,3 IC Address h4C,4D,4E,4F; CPU Address:h116, 117, 118, 119) PVMAP06_0,1,3 IC Address h50,51,52,53; CPU Address:h11A, 11B, 11C, 11D) PVMAP07_0,1,3 IC Address h54,55,56,57; CPU Address:h11E, 11F, 120, 121) PVMAP08_0,1,3 IC Address h58,59,5A,5B; CPU Address:h122, 123, 124, 125) PVMAP09_0,1,3 IC Address h5C,5D,5E,5F; CPU Address:h126, 127, 128, 129) PVMAP10_0,1,3 IC Address h60,61,62,63; CPU Address:h12A, 12B, 12C, 12D) PVMAP11_0,1,3 IC Address h64,65,66,67; CPU Address:h12E, 12F, 130, 131) PVMAP12_0,1,3 IC Address h68,69,6A,6B; CPU Address:h132, 133, 134, 135) PVMAP13_0,1,3 IC Address h6C,6D,6E,6F; CPU Address:h136, 137, 138, 139) PVMAP14_0,1,3 IC Address h70,71,72,73; CPU Address:h13A, h13B, 13C, 13D) PVMAP15_0,1,3 IC Address h74,75,76,77; CPU Address:h13E, 13F, 140, 141) PVMAP25_0,1,3 IC Address h9C,9D,9E,9F; CPU Address:h166, 167, 168, 169) (Gigabit port 1) PVMAP26_0,1,3 IC Address hA0,A1,A2,A3; CPU Address:h16A, 16B, 16C, 16D) (Gigabit port 2) 13.4.1 PVMODE IC Address: h0A4, CPU Address:h170 Accessed by CPU, serial interface (R/W) 7 5 4 SMO 3 2 DL 1 SL 0 Bit [0]: * Reserved - Must be `0' Slow learning (Default = 0) Same function as SE_OP MODE bit 7. Either bit can enable the function; both need to be turned off to disable the feature. Disable dropping frames with destination MAC addresses 0180C2000001 to 0180C200000F (Default = 0) 0: Drop all frames in the range 1: Treats frames as multicast Bit [1]: * Bit [2]: * 52 Zarlink Semiconductor Inc. Data Sheet Bit [3]: Bit [4]: * * Reserved Support MAC address 0 (Default = 0) - 0: MAC address 0 is not learned. Bit [7:5]: * 1: MAC address 0 is learned. ZL50417 Reserved 13.5 (Group 2 Address) Port Trunking Groups Trunk Group 0 - Up to four 10/100 ports can be selected for trunk group 0. 13.5.1 TRUNK0_MODE- Trunk group 0 mode IC Address h0A5; CPU Address:203 Accessed by serial interface and IC (R/W) 7 4 3 Hash Select Bit [1:0]: * 2 1 Port Select 0 Port selection in unmanaged mode. Input pin TRUNK0 enable/disable trunk group 0 in unmanaged mode. 00 Reserved 01 Port 0 and 1 are used for trunk0 10 Port 0,1 and 2 are used for trunk0 11 Port 0,1,2 and 3 are used for trunk0 Bit [3:2] * Hash Select. The Hash selected is valid for Trunk 0, 1 and 2. (Default 00) - 00 Use Source and Destination Mac Address for hashing 01 Use Source Mac Address for hashing 10 Use Destination Mac Address for hashing 11 Use source destination MAC address and ingress physical port number for hashing 13.5.2 TRUNK1_MODE - Trunk group 1 mode IC Address h0A6; CPU Address:20B Accessed by serial interface and IC (R/W) 7 2 1 0 Port Select Zarlink Semiconductor Inc. 53 ZL50417 Bit [1:0]: * Port selection in unmanaged mode. Input pin TRUNK1 enable/disable trunk group 1 in unmanaged mode. Trunk Group 2 00 Reserved 01 Port 4 and 5 are used for trunk1 10 Reserved 11 Port 4,5,6 and 7 are used for trunk1 Data Sheet 13.5.3 TRUNK2_MODE - Trunk group 2 mode (Gigabit ports 1 and 2) CPU Address:210 Accessed by serial interface (R/W) 7 6 4 3 0 Ring/trunk Mode Bit [3:0] Bit [6:4] * * * Reserved 000 Normal 001 Trunk Mode. Enable Trunk group for Gigabit port 1 and 2 in managed mode. In unmanaged mode Trunk 2 is enable/disable using input pin TRUNK2. 010 Single Ring with G1 100 Single Ring with G2 111 Dual Ring Mode * * * 13.5.4 RQSS - Receive Queue Status CPU Address:h324 Accessed by serial interface (RO) 7 6 5 Tx Queue Agent Bit[5:0]: Unit of 100ms (Default 8) Disable transmission queue aging if value is zero. Aging timer for all ports and queues. This register must be set to 0 for `No Packet Loss Flow Control Test'. 0 54 Zarlink Semiconductor Inc. Data Sheet 13.6 13.6.1 (Group 4 Address) Search Engine Group AGETIME_LOW - MAC address aging time Low ZL50417 IC Address h0A8; CPU Address:h400 Accessed by serial interface and IC (R/W) Bit [7:0] Low byte of the MAC address aging timer MAC address aging is enable/disable by boot strap TSTOUT9 13.6.2 AGETIME_HIGH -MAC address aging time High IC Address h0A9; CPU Address h401 Accessed by serial interface and IC (R/W) Bit [7:0]: High byte of the MAC address aging timer. The default setting provide 300 seconds aging time. Aging time is based on the following equation: {AGETIME_TIME,AGETIME_LOW} X (# of MAC entries in the memory X100sec). Number of MAC entries = 32K when 1 MB is used per Bank. Number of entries = 64K when 2 MB is used per Bank. 13.6.3 SE_OPMODE - Search Engine Operation Mode CPU Address:h403 Accessed by serial interface (R/W) {SE_OPMODE} X(# of entries 100usec) 7 SL Bit [5:0]: Bit [6]: * * Reserved Disable MCT speedup aging (Default 0) - 1 - Disable speedup aging when MCT resource is low. Bit [7]: * 0 - Enable speedup aging when MCT resource is low. 6 DMS 5 0 Slow Learning (Default 0) - 1- Enable slow learning. Learning is temporary disabled when search demand is high 0 - Learning is performed independent of search demand Zarlink Semiconductor Inc. 55 ZL50417 13.7 13.7.1 (Group 5 Address) Buffer Control/QOS Group FCBAT - FCB Aging Timer Data Sheet IC Address h0AA; CPU Address:h500 7 FCBAT Bit [7:0]: * * FCB Aging time. Unit of 1ms. (Default FF) This is for buffer aging control. It is used to configure the buffer aging time. This function can be enabled/disabled through bootstrap pin. It is not suggested to use this function for normal operation. 0 13.7.2 QOSC - QOS Control IC Address h0AB; CPU Address:h501 Accessed by serial interface and IC (R/W) 7 Tos-d Bit [0]: Bit [4]: * * * * Bit [5]: Bit [6]: * * * Bit [7]: * * * 6 Tos-p 5 4 VF1c 3 1 0 L QoS frame lost is OK. Priority will be available for flow control enabled source only when this bit is set (Default 0) Per VLAN Multicast Flow Control (Default 0) 0 - Disable 1 - Enable Reserved Select TOS bits for Priority (Default 0) 0 - Use TOS [4:2] bits to map the transmit priority 1 - Use TOS [7:5] bits to map the transmit priority Select TOS bits for Drop priority (Default 0) 0 - Use TOS [4:2] bits to map the drop priority 1 - Use TOS [7:5] bits to map the drop priority 13.7.3 FCR - Flooding Control Register IC Address h0AC; CPU Address:h502 Accessed by serial interface and IC (R/W) 7 Tos 6 TimeBase 4 3 U2MR 0 56 Zarlink Semiconductor Inc. Data Sheet Bit [3:0]: * ZL50417 U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used to limit the amount of flooding traffic. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 8) Bit [6:4]: Time Base: (Default = 000) - 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 100us, same as 000. Bit [7]: Select VLAN tag or TOS (IP packets) to be preferentially picked to map transmit priority and drop priority (Default = 0). - 0 - Select VLAN Tag priority field over TOS 1 - Select TOS over VLAN tag priority field 13.7.4 AVPML - VLAN Priority Map IC Address h0AD; CPU Address:h503 Accessed by serial interface and IC (R/W) 7 VP2 6 5 VP1 3 2 VP0 0 Registers AVPML, AVPMM, and AVPMH allow the eight VLAN Tag priorities to map into eight Internal level transmit priorities. Under the Internal transmit priority, Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit priorities. Under the internal transmit priority, seven is highest priority where as zero is the lowest. This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map VLAN priority 0 into internal transmit priority 7. The new priority is used inside the ZL50417. When the packet goes out it carries the original priority. Bit [2:0]: Bit [5:3]: Bit [7:6]: Priority when the VLAN tag priority field is 0 (Default 0) Priority when the VLAN tag priority field is 1 (Default 0) Priority when the VLAN tag priority field is 2 (Default 0) Zarlink Semiconductor Inc. 57 ZL50417 13.7.5 AVPMM - VLAN Priority Map Data Sheet IC Address h0AE, CPU Address:h504 Accessed by serial interface and IC (R/W) Map VLAN priority into eight level transmit priorities: 7 VP5 Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: 6 VP4 4 3 VP3 1 0 VP2 Priority when the VLAN tag priority field is 2 (Default 0) Priority when the VLAN tag priority field is 3 (Default 0) Priority when the VLAN tag priority field is 4 (Default 0) Priority when the VLAN tag priority field is 5 (Default 0) 13.7.6 AVPMH - VLAN Priority Map IC Address h0AF, CPU Address:h505 Accessed by serial interface and IC (R/W) 7 VP7 Map VLAN priority into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: Priority when the VLAN tag priority field is 5 (Default 0) Priority when the VLAN tag priority field is 6 (Default 0) Priority when the VLAN tag priority field is 7 (Default 0) 5 4 VP6 2 1 VP5 0 13.7.7 TOSPML - TOS Priority Map IC Address h0B0, CPU Address:h506 Accessed by serial interface and IC (R/W) 7 6 TP2 5 TP1 3 2 TP0 0 Map TOS field in IP packet into eight level transmit priorities Bit [2:0]: Bit [5:3]: Bit [7:6]: Priority when the TOS field is 0 (Default 0) Priority when the TOS field is 1 (Default 0) Priority when the TOS field is 2 (Default 0) 58 Zarlink Semiconductor Inc. Data Sheet 13.7.8 TOSPMM - TOS Priority Map IC Address h0B1, CPU Address:h507 Accessed by serial interface and IC (R/W) 7 TP5 6 TP4 4 3 TP3 1 0 TP2 ZL50417 Map TOS field in IP packet into eight level transmit priorities Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: Priority when the TOS field is 2 (Default 0) Priority when the TOS field is 3 (Default 0) Priority when the TOS field is 4 (Default 0) Priority when the TOS field is 5 (Default 0) 13.7.9 TOSPMH - TOS Priority Map IC Address h0B2, CPU Address:h508 Accessed by serial interface and IC (R/W) 7 TP7 5 4 TP6 2 TP5 0 Map TOS field in IP packet into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: Priority when the TOS field is 5 (Default 0) Priority when the TOS field is 6 (Default 0) Priority when the TOS field is 7 (Default 0) 13.7.10 AVDM - VLAN Discard Map IC Address h0B3, CPU Address:h509 Accessed by serial interface and IC (R/W) 7 FDV7 6 FDV6 5 FDV5 4 FDV4 3 FDV3 2 FDV2 1 FDV1 0 FDV0 Map VLAN priority into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Frame drop priority when VLAN Tag priority field is 0 (Default 0) Frame drop priority when VLAN Tag priority field is 1 (Default 0) Frame drop priority when VLAN Tag priority field is 2 (Default 0) Frame drop priority when VLAN Tag priority field is 3 (Default 0) Frame drop priority when VLAN Tag priority field is 4 (Default 0) Zarlink Semiconductor Inc. 59 ZL50417 Bit [5]: Bit [6]: Bit [7]: Frame drop priority when VLAN Tag priority field is 5 (Default 0) Frame drop priority when VLAN Tag priority field is 6 (Default 0) Frame drop priority when VLAN Tag priority field is 7 (Default 0) Data Sheet 13.7.11 TOSDML - TOS Discard Map IC Address h0B4, CPU Address:h50A Accessed by serial interface and IC (R/W) 7 FDT7 6 FDT6 5 FDT5 4 FDT4 3 FDT3 2 FDT2 1 FDT1 0 FDT0 Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Frame drop priority when TOS field is 0 (Default 0) Frame drop priority when TOS field is 1 (Default 0) Frame drop priority when TOS field is 2 (Default 0) Frame drop priority when TOS field is 3 (Default 0) Frame drop priority when TOS field is 4 (Default 0) Frame drop priority when TOS field is 5 (Default 0) Frame drop priority when TOS field is 6 (Default 0) Frame drop priority when TOS field is 7 (Default 0) 13.7.12 BMRC - Broadcast/Multicast Rate Control IC Address h0B5, CPU Address:h50B) Accessed by serial interface and IC (R/W) 7 Broadcast Rate 4 3 Multicast Rate 0 This broadcast and multicast rate defines for each port, the number of packets allowed to be forwarded within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Time base is based on register FCR [6:4] Bit [3:0]: Bit [7:4]: Multicast Rate Control. Number of multicast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0). Broadcast Rate Control. Number of broadcast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0) 60 Zarlink Semiconductor Inc. Data Sheet 13.7.13 UCC - Unicast Congestion Control IC Address h0B6, CPU Address: 50C Accessed by serial interface and IC (R/W) 7 Unicast congest threshold Bit [7:0]: 0 ZL50417 Number of frame count. Used for best effort dropping at B% when destination port's best effort queue reaches UCC threshold and shared pool is all in use. Granularity 1 frame. (Default: h10 for 2 MB/bank or h08 for 1 MB/bank) 13.7.14 MCC - Multicast Congestion Control IC Address h0B7, CPU Address: 50D Accessed by serial interface and IC (R/W) 7 5 4 Multicast congest threshold 0 FC reaction period Bit [4:0]: In multiples of two frames (granularity). Used for triggering MC flow control when destination port's multicast best effort queue reaches MCC threshold.(Default 0x10) Flow control reaction period (Default 2) Granularity 4uSec. Bit [7:5]: 13.7.15 PR100 - Port Reservation for 10/100 ports IC Address h0B8, CPU Address 50E Accessed by serial interface and IC (R/W) 7 Buffer low threshold Bit [3:0]: 4 3 0 SP Buffer reservation Per source port buffer reservation. Define the space in the FDB reserved for each 10/100 port and CPU. Expressed in multiples of 4 packets. For each packet 1536 bytes are reserved in the memory. Expressed in multiples of 4 packets. Threshold for dropping all best effort frames when destination port best efforts queues reaches UCC threshold, shared pool is all used and source port reservation is at or below the PR100[7:4] level. Also the threshold for initiating UC flow control. * Default: h36 for 16+2 configuration with memory 2MB/bank; h24 for 16+2 configuration with 1MB/bank; Bits [7:4]: Zarlink Semiconductor Inc. 61 ZL50417 13.7.16 PRG - Port Reservation for Giga ports Data Sheet IC Address h0B9, CPU Address 50F Accessed by serial interface and IC (R/W) 7 Buffer low threshold Bit [3:0]: 4 3 0 SP buffer reservation Per source port buffer reservation. Define the space in the FDB reserved for each Gigabit port. Expressed in multiples of 16 packets. For each packet 1536 bytes are reserved in the memory. Expressed in multiples of 16 packets. Threshold for dropping all best effort frames when destination port best effort queues reach UCC threshold, shared pool is all used and source port reservation is at or below the PRG[7:4] level. Also the threshold for initiating UC flow control. * Default: - H58 for memory 2MB/bank; H35 for 1MB/bank; Bits [7:4]: 13.7.17 SFCB - Share FCB Size IC Address h0BA), CPU Address 510 Accessed by serial interface and IC (R/W) 7 Shared pool buffer size Bits [7:0]: Expressed in multiples of 4 packets. Buffer reservation for shared pool. * Default: - h64 for 16+2 configuration with memory of 2MB/bank; h14 for 16+2 configuration with memory of 1MB/bank; 0 13.7.18 C2RS - Class 2 Reserve Size IC Address h0BB, CPU Address 511 Accessed by serial interface and IC (R/W) 7 Class 2 FCB Reservation Buffer reservation for class 2 (third lowest priority). Granularity 1. (Default 0) 0 62 Zarlink Semiconductor Inc. Data Sheet 13.7.19 C3RS - Class 3 Reserve Size IC Address h0BC, CPU Address 512 Accessed by serial interface and IC (R/W) 7 Class 3 FCB Reservation Buffer reservation for class 3. Granularity 1. (Default 0) 0 ZL50417 13.7.20 C4RS - Class 4 Reserve Size IC Address h0BD, CPU Address 513 Accessed by serial interface and IC (R/W) 7 Class 4 FCB Reservation Buffer reservation for class 4. Granularity 1. (Default 0) 0 13.7.21 C5RS - Class 5 Reserve Size IC Address h0BE; CPU Address 514 Accessed by serial interface and IC (R/W) 7 Class 5 FCB Reservation Buffer reservation for class 5. Granularity 1. (Default 0) 0 13.7.22 C6RS - Class 6 Reserve Size IC Address h0BF; CPU Address 515 Accessed by serial interface and IC (R/W) 7 Class 6 FCB Reservation Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0) 0 Zarlink Semiconductor Inc. 63 ZL50417 13.7.23 C7RS - Class 7 Reserve Size Data Sheet IC Address h0C0; CPU Address 516 Accessed by serial interface and IC (R/W) 7 Class 7 FCB Reservation Buffer reservation for class 7 (highest priority). Granularity 1. (Default 0) 0 13.7.24 QOSCn - Classes Byte Limit Set 0 Accessed by serial interface and IC (R/W): C -- QOSC00 - BYTE_C01 (IC Address h0C1, CPU Address 517) B -- QOSC01 - BYTE_C02 (IC Address h0C2, CPU Address 518) A -- QOSC02 - BYTE_C03 (IC Address h0C3, CPU Address 519) QOSC00 through QOSC02 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Drop (WRED) Scheme described in Chapter 7. There are four such sets of values A-C specified in Classes Byte Limit Set 0, 1, 2, and 3. Each 10/ 100 port can choose one of the four Byte Limit Sets as specified by the QoS Select field located in bits 5 to 4 of the ECR2n register. The values A-C are per-queue byte thresholds for random early drop. QOSC02 represents A, and QOSC00 represents C. Granularity when Delay bound is used: QOSC02: 128 bytes, QOSC01: 256 bytes, QOSC00: 512 bytes. Granularity when WFQ is used: QOSC02: 512 bytes, QOSC01: 512 bytes, QOSC00: 512 bytes. 13.7.25 Classes Byte Limit Set 1 Accessed by serial interface and IC (R/W): C - QOSC03 - BYTE_C11 (IC Address h0C4, CPU Address 51a) B - QOSC04 - BYTE_C12 (IC Address h0C5, CPU Address 51b) A - QOSC05 - BYTE_C13 (IC Address h0C6, CPU Address 51c) QOSC03 through QOSC05 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC05: 128 bytes, QOSC04: 256 bytes. QOSC03: 512 bytes. Granularity when WFQ is used: QOSC05: 512 bytes, QOSC04: 512 bytes, QOSC03: 512 bytes. 13.7.26 Classes Byte Limit Set 2 Accessed by serial interface (R/W): C - QOSC06 - BYTE_C21 (CPU Address 51d) B - QOSC07 - BYTE_C22 (CPU Address 51e) A - QOSC08 - BYTE_C23 (CPU Address 51f) QOSC06 through QOSC08 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. 64 Zarlink Semiconductor Inc. Data Sheet ZL50417 Granularity when Delay bound is used: QOSC08: 128 bytes, QOSC07: 256 bytes. QOSC06: 512 bytes. Granularity when WFQ is used: QOSC08: 512 bytes, QOSC07: 512 bytes, QOSC06: 512 bytes. 13.7.27 Classes Byte Limit Set 3 Accessed by serial interface (R/W): C - QOSC09 - BYTE_C31 (CPU Address 520) B - QOSC10 - BYTE_C32 (CPU Address 521) A - QOSC11 - BYTE_C33 (CPU Address 522) QOSC09 through QOSC011 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Drop (WRED) scheme. Granularity when Delay bound is used: QOSC11: 128 bytes, QOSC10: 256 bytes, QOSC09: 512 bytes. Granularity when WFQ is used: QOSC11: 512 bytes, QOSC10: 512 bytes, QOSC09: 512 bytes 13.7.28 Classes Byte Limit Giga Port 1 Accessed by serial interface and IC (R/W): F - QOSC12 - BYTE_C2_G1 (IC Address h0C7, CPU Address 523) E - QOSC13 - BYTE_C3_G1 (IC Address h0C8, CPU Address 524) D - QOSC14 - BYTE_C4_G1 (IC Address h0C9, CPU Address 525) C -QOSC15 - BYTE_C5_G1 (IC Address h0CA, CPU Address 526) B - QOSC16 - BYTE_C6_G1 (IC Address h0CB, CPU Address 527) A - QOSC17 - BYTE_C7_G1 (IC Address h0CC, CPU Address 528) QOSC12 through QOSC17 represent the values A-F for Gigabit port 1. They are per-queue byte thresholds for random early drop. QOSC17 represents A, and QOSC12 represents F. Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes, QOSC13 and QOSC12: 1024 bytes. Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes 13.7.29 Classes Byte Limit Giga Port 2 Accessed by serial interface and IC (R/W) F - QOSC18 - BYTE_C2_G2 (IC Address h0CD, CPU Address 529) E - QOSC19 - BYTE_C3_G2 (IC Address h0CE, CPU Address 52a) D - QOSC20 - BYTE_C4_G2 (IC Address h0CF, CPU Address 52b) C - QOSC21 - BYTE_C5_G2 (IC Address h0D0, CPU Address 52c) B - QOSC22 - BYTE_C6_G2 (IC Address h0D1, CPU Address 52d) A - QOSC23 - BYTE_C7_G2 (IC Address h0D2, CPU Address 52e) QOSC12 through QOSC17 represent the values A-F for Gigabit port 2. They are per-queue byte thresholds for random early drop. QOSC17 represents A, and QOSC12 represents F. Zarlink Semiconductor Inc. 65 ZL50417 Data Sheet Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes, QOSC13 and QOSC12: 1024 bytes. Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes 13.7.30 Classes WFQ Credit Set 0 Accessed by serial interface W3 - QOSC24[5:0] - CREDIT_C00 (CPU Address 52f) W2 - QOSC25[5:0] - CREDIT_C01 (CPU Address 530) W1 - QOSC26[5:0] - CREDIT_C02 (CPU Address 531) W0 - QOSC27[5:0] - CREDIT_C03 (CPU Address 532) QOSC24 through QOSC27 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC27 corresponds to W0, and QOSC24 corresponds to W3. QOSC24[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC25[7]: Priority service allow flow control for the ports select this parameter set. QOSC25[6]: Flow control pause best effort traffic only Both flow control allow and flow control best effort only can take effect only the priority type is WFQ. 13.7.31 Classes WFQ Credit Set 1 Accessed by serial interface W3 - QOSC28[5:0] - CREDIT_C10 (CPU Address 533) W2 - QOSC29[5:0] - CREDIT_C11 (CPU Address 534) W1 - QOSC30[5:0] - CREDIT_C12 (CPU Address 535) W0 - QOSC31[5:0] - CREDIT_C13 (CPU Address 536) QOSC28 through QOSC31 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC31 corresponds to W0, and QOSC28 corresponds to W3. QOSC28[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC29[7]: Priority service allow flow control for the ports select this parameter set. QOSC29[6]: Flow control pause best effort traffic only 13.7.32 Classes WFQ Credit Set 2 Accessed by serial interface W3 - QOSC32[5:0] - CREDIT_C20 (CPU Address 537) W2 - QOSC33[5:0] - CREDIT_C21 (CPU Address 538) W1 - QOSC34[5:0] - CREDIT_C22 (CPU Address 539) W0 - QOSC35[5:0] - CREDIT_C23 (CPU Address 53a) 66 Zarlink Semiconductor Inc. Data Sheet ZL50417 QOSC35 through QOSC32 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC35 corresponds to W0, and QOSC32 corresponds to W3. QOSC32[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC33[7]: Priority service allow flow control for the ports select this parameter set. QOSC33[6]: Flow control pause for best effort traffic only 13.7.33 Classes WFQ Credit Set 3 Accessed by serial interface W3 - QOSC36[5:0] - CREDIT_C30 (CPU Address 53b) W2 - QOSC37[5:0] - CREDIT_C31 (CPU Address 53c) W1 - QOSC38[5:0] - CREDIT_C32 (CPU Address 53d) W0 - QOSC39[5:0] - CREDIT_C33 (CPU Address 53e) QOSC39 through QOSC36 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC39 corresponds to W0, and QOSC36 corresponds to W3. QOSC36[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC37[7]: Priority service allow flow control for the ports select this parameter set. QOSC37[6]: Flow control pause best effort traffic only 13.7.34 Classes WFQ Credit Port G1 Accessed by serial interface W7 - QOSC40[5:0] - CREDIT_C0_G1(CPU Address 53f) [7:6]: Priority service type. Option 1 to 4. W6 - QOSC41[5:0] - CREDIT_C1_G1 (CPU Address 540) [7]: Priority service allow flow control for the ports select this parameter set. [6]: Flow control pause best effort traffic only W5 - QOSC42[5:0] - CREDIT_C2_G1 (CPU Address 541) W4 - QOSC43[5:0] - CREDIT_C3_G1 (CPU Address 542) W3 - QOSC44[5:0] - CREDIT_C4_G1 (CPU Address 543) W2 - QOSC45[5:0] - CREDIT_C5_G1 (CPU Address 544) W1 - QOSC46[5:0] - CREDIT_C6_G1 (CPU Address 545) W0 - QOSC47[5:0] - CREDIT_C7_G1 (CPU Address 546) QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. The granularity of the numbers is 1, and their sum must be 64. QOSC47 corresponds to W0, and QOSC40 corresponds to W7. Zarlink Semiconductor Inc. 67 ZL50417 13.7.35 Classes WFQ Credit Port G2 Data Sheet Accessed by serial interface W7 - QOSC48[5:0] - CREDIT_C0_G2(CPU Address 547) [7:6]: Priority service type. Option 1 to 4 W6 - QOSC49[5:0] - CREDIT_C1_G2(CPU Address 548) [7]: Priority service allow flow control for the ports select this parameter set. [6]: Flow control pause best effort traffic only W5 - QOSC50[5:0] - CREDIT_C2_G2(CPU Address 549) W4 - QOSC51[5:0] - CREDIT_C3_G2(CPU Address 54a) W3 - QOSC52[5:0] - CREDIT_C4_G2(CPU Address 54b) W2 - QOSC53[5:0] - CREDIT_C5_G2(CPU Address 54c) W1 - QOSC54[5:0] - CREDIT_C6_G2(CPU Address 54d) W0 - QOSC55[5:0] - CREDIT_C7_G2(CPU Address 54e) QOSC48 through QOSC55 represents the set of WFQ parameters for Gigabit port 2. The granularity of the numbers is 1, and their sum must be 64. QOSC55 corresponds to W0, and QOSC48 corresponds to W7. 13.7.36 Class 6 Shaper Control Port G1 Accessed by serial interface QOSC56[5:0] - TOKEN_RATE_G1 (CPU Address 54f). Programs de average rate for gigabit port 1. When equal to 0, shaper is disable. Granularity is 1. QOSC57[7:0] - TOKEN_LIMIT_G1 (CPU Address 550). Programs the maximum counter for gigabit port 1. Granularity is 16 bytes. Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is limited to gigabit ports and queue P6 when it is in strict priority. QOSC41 programs the peak rate for gigabit port 1. See Programming QoS Registers application note for more information 13.7.37 Class 6 Shaper Control Port G2 Accessed by serial interface QOSC58[5:0] - TOKEN_RATE_G2 (CPU Address 551). Programs de average rate for gigabit port 2. When equal to 0, shaper is disable. Granularity is 1. QOSC59[7:0] - TOKEN_LIMIT_G2 (CPU Address 552). Programs the maximum counter for gigabit port 2. Granularity is 16 bytes. Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is limited to gigabit ports and queue P6 when it is in strict priority. QOSC49 programs the peak rate for gigabit port 2. See Programming QoS Register application note for more information. 68 Zarlink Semiconductor Inc. Data Sheet 13.7.38 RDRC0 - WRED Rate Control 0 IC Address 0FB, CPU Address 553 Accessed by Serial Interface and IcC (R/W) 7 X Rate Bits [7:4]: Bits[3:0]: 4 3 Y Rate 0 ZL50417 Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%. Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%. See Programming QoS Registers application note for more information 13.7.39 RDRC1 - WRED Rate Control 1 IC Address 0FC, CPU Address 554 Accessed by Serial Interface and IC (R/W) 7 Z Rate Bits [7:4]: Bits[3:0]: 4 3 B Rate 0 Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%. Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and destination port best effort queue reaches UCC. Granularity 6.25%. See Programming QoS Registers application note for more information 13.7.40 User Defined Logical Ports and Well Known Ports The ZL50417 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: * * * * * * * * 0:23 1:512 2:6000 3:443 4:111 5:22555 6:22 7:554 Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_ Enable can individually turn on/off each Well Known Port if desired. Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7 Zarlink Semiconductor Inc. 69 ZL50417 Data Sheet registers. Two registers are required to be programmed for the logical port number. The respective priority can be programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in RPRIORITY. 13.7.40.1 USER_PORT0_(0~7) - User Define Logical Port (0~7) USER_PORT_0 - IC Address h0D6 + 0DE; CPU Address 580(Low) + 581(high) USER_PORT_1 - IC Address h0D7 + 0DF; CPU Address 582 + 583 USER_PORT_2 - IC Address h0D8 + 0E0; CPU Address 584 + 585 USER_PORT_3 - IC Address h0D9 + 0E1; CPU Address 586 + 587 USER_PORT_4 - IC Address h0DA + 0E2; CPU Address 588 + 589 USER_PORT_5 - IC Address h0DB + 0E3; CPU Address 58A + 58B USER_PORT_6 - IC Address h0DC + 0E4; CPU Address 58C + 58D USER_PORT_7 - IC Address h0DD + 0E5; CPU Address 58E + 58F Accessed by CPU, serial interface and IC (R/W) 7 TCP/UDP Logic Port Low 7 TCP/UDP Logic Port High (Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define eight separate ports. 0 0 13.7.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority IC Address h0E6, CPU Address 590 Accessed by serial interface and IC (R/W) 7 Priority 1 The chip allows the CPU to define the priority Bits[3:0]: Bits [7:4]: Priority setting, transmission + dropping, for logic port 0 Priority setting, transmission + dropping, for logic port 1 (Default 00) 5 4 Drop 3 Priority 0 1 0 Drop 70 Zarlink Semiconductor Inc. Data Sheet 13.7.40.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority IC Address h0E7, CPU Address 591 Accessed by serial interface and IC (R/W) 7 Priority 3 5 4 Drop 3 Priority 2 1 0 Drop ZL50417 13.7.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority IC Address h0E8, CPU Address 592 Accessed by serial interface and IC (R/W) 7 Priority 5 (Default 00) 5 4 Drop 3 Priority 4 1 0 Drop 13.7.40.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority IC Address h0E9, CPU Address 593 Accessed by serial interface and IC (R/W) 7 Priority 7 (Default 00) 5 4 Drop 3 Priority 6 1 0 Drop 13.7.40.6 USER_PORT_ENABLE[7:0] - User Define Logic 7 to 0 Port Enables IC Address h0EA, CPU Address 594 Accessed by serial interface and IC (R/W) 7 P7 (Default 00) 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0 Zarlink Semiconductor Inc. 71 ZL50417 13.7.40.7 Data Sheet WELL_KNOWN_PORT[1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority IC Address h0EB, CPU Address 595 Accessed by serial interface and IC (R/W) 7 Priority 1 5 4 Drop 3 Priority 0 1 0 Drop Priority 0 - Well known port 23 for telnet applications. Priority 1 - Well Known port 512 for TCP/UDP. (Default 00) 13.7.40.8 WELL_KNOWN_PORT[3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority IC Address h0EC, CPU Address 596 Accessed by serial interface and IC (R/W) 7 Priority 3 Priority 2 - Well known port 6000 for XWIN. Priority 3 - Well known port 443 for http.sec (Default 00) 5 4 Drop 3 Priority 2 1 0 Drop 13.7.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority IC Address h0ED, CPU Address 597 Accessed by serial interface and IC (R/W) 7 Priority 5 5 4 Drop 3 Priority 4 1 0 Drop Priority 4 - Well Known port 111 for sun remote procedure call. Priority 5 - Well Known port 22555 for IP Phone call setup. (Default 00) 13.7.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority IC Address h0EE, CPU Address 598 Accessed by serial interface and IC (R/W) 7 Priority 7 Priority 6 - well know port 22 for ssh. Priority 7 - well Known port 554 for rtsp. (Default 00) 72 Zarlink Semiconductor Inc. 5 4 Drop 3 Priority 6 1 0 Drop Data Sheet 13.7.40.11 IC Address h0EF, CPU Address 599 Accessed by serial interface and IC (R/W) 7 P7 1 - Enable 0 - Disable 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0 ZL50417 WELL KNOWN_PORT_ENABLE [7:0] - Well Known Logic 7 to 0 Port Enables (Default 00) 13.7.40.12 RLOWL - User Define Range Low Bit 7:0 IC Address h0F4, CPU Address: 59a Accessed by serial interface and IC (R/W) (Default 00) 13.7.40.13 1RLOWH - User Define Range Low Bit 15:8 IC Address h0F5, CPU Address: 59b Accessed by serial interface and IC (R/W) (Default 00) 13.7.40.14 RHIGHL - User Define Range High Bit 7:0 IC Address h0D3, CPU Address: 59c Accessed by CPU, serial interface and IC (R/W) (Default 00) 13.7.40.15 RHIGHH - User Define Range High Bit 15:8 IC Address h0D4, CPU Address: 59d Accessed by serial interface and IC (R/W) (Default 00) 13.7.40.16 RPRIORITY - User Define Range Priority IC Address h0D5, CPU Address: 59e Accessed by serial interface and IC (R/W) 7 4 3 Range Transmit Priority 0 Drop Zarlink Semiconductor Inc. 73 ZL50417 Data Sheet RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit[3:1] Bits[0]: Transmit Priority Drop Priority 13.8 13.8.1 (Group 6 Address) MISC Group MII_OP0 - MII Register Option 0 IC Address F0, CPU Address:h600 Accessed by serial interface and IC (R/W) 7 hfc Bits [7]: 6 1prst 5 DisJ 4 Vendor Spc. Reg Addr 0 Half duplex flow control feature 0 = Half duplex flow control always enable 1 = Half duplex flow control by negotiation Link partner reset auto-negotiate disable Disable jabber detection. This is for HomePNA applications or any serial operation slower than 10Mbps. 0 = Enable 1 = Disable Vendor specified link status register address (null value means don't use it) (Default 00). This is used if the Linkup bit position in the PHY is non-standard Bits[6]: Bits[5]: Bit[4:0]: 13.8.2 MII_OP1 - MII Register Option 1 IC Address F1, CPU Address:h601 Accessed by serial interface and IC (R/W) 7 Speed bit location Bits[3:0]: Bits [7:4]: 4 3 Duplex bit location 0 Duplex bit location in vendor specified register Speed bit location in vendor specified register (Default 00) 74 Zarlink Semiconductor Inc. Data Sheet 13.8.3 FEN - Feature Register IC Address F2, CPU Address:h602) Accessed by serial interface and IC (R/W) 7 DML Bits [1:0]: Bit [2]: 6 Mii 5 3 2 DS 1 0 ZL50417 Reserved (Default 0) Support DS EF Code. (Default 0) - 0 - Disable 1 - Enable (all ports) When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set for 0. Bit [5:3]: Bit [6]: Reserved (Default 010) Disable MII Management State Machine (Default 0) - 0: Enable MII Management State Machine 1: Disable MII Management State Machine Bit [7]: Disable using MCT Link List structure (Default 0) - 0 - Enable using MCT Link structure 1 - Disable using MCT Link List structure 13.8.4 MIIC0 - MII Command Register 0 CPU Address:h603 Accessed by serial interface only (R/W) Bit [7:0] - MII Data [7:0] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 13.8.5 MIIC1 - MII Command Register 1 CPU Address:h604 Accessed by serial interface only (R/W) Bit [7:0] - MII Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Zarlink Semiconductor Inc. 75 ZL50417 13.8.6 MIIC2 - MII Command Register 2 CPU Address:h605 Accessed by serial interface only (R/W) 7 6 Mii OP Bit [4:0] Bit [6:5] 5 4 Register address 0 Data Sheet REG_AD - Register PHY Address OP - Operation code "10" for read command and "01" for write command Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 13.8.7 MIIC3 - MII Command Register 3 CPU Address:h606 Accessed by serial interface only (R/W) 7 Rdy Bits [4:0] Bit [6] Bit [7] 6 Valid 5 4 0 PHY address PHY_AD - 5 Bit PHY Address VALID - Data Valid from PHY (Read Only) RDY - Data is returned from PHY (Ready Only) Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Writing this register will initiate a serial management cycle to the MII management interface. 13.8.8 MIID0 - MII Data Register 0 CPU Address:h607 Accessed by serial interface only (RO) Bit [7:0] - MII Data [7:0] 13.8.9 MIID1 - MII Data Register 1 CPU Address:h608 Accessed by serial interface only (RO) Bit [7:0] - MII Data [15:8] 76 Zarlink Semiconductor Inc. Data Sheet 13.8.10 LED Mode - LED Control CPU Address:h609 Accessed by CPU, serial interface and IC (R/W) 7 5 4 3 2 1 0 ZL50417 Clock rate Bit [0] Bit[2:1]: Reserved (Default 0) Hold time for LED signal (Default 00) 00=8msec 01=16msec 10=32msec 11=64msec LED clock frequency (Default 0) 00=100M/8=12.5 MHz 01=100M/16= 25 MHz 10=100M/32= 125 MHz 11=100M/64=1.5625 MHz Hold Time - Bit[4:3]: - Bit[7:5]: Reserved. Must be set to `0' (Default 0) 13.8.11 CHECKSUM - EEPROM Checksum IC Address FF, CPU Address:h60b Accessed by serial interface and IC (R/W) Bit [7:0]: (Default 0) This register is used in unmanaged mode only. Before requesting that the ZL50417 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. The checksum formula is: FF IC register = 0 i=0 When the ZL50417 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50417 does not start and pin CHECKSUM_OK is set to zero. Zarlink Semiconductor Inc. 77 ZL50417 13.9 13.9.1 (Group 7 Address) Port Mirroring Group MIRROR1_SRC - Port Mirror source port Data Sheet CPU Address 700 Accessed by serial interface (R/W) (Default 7F) 7 6 5 I/O Bit [4:0]: Bit [5]: Bit [6]: Bit [7]: 4 Src Port Select 0 Source port to be mirrored. Use illegal port number to disable mirroring 1 - select ingress data 0 - select egress data Reserved Reserved must be se to '1' 13.9.2 MIRROR1_DEST - Port Mirror destination CPU Address 701 Accessed by serial interface (R/W) (Default 17) 7 5 4 Dest Port Select Bit [4:0]: Port Mirror Destination When port mirroring is enable, destination port can not serve as a data port. 0 13.9.3 MIRROR2_SRC - Port Mirror source port CPU Address 702 Accessed by serial interface (R/W) (Default FF) 7 6 5 I/O Bit [4:0]: Bit [5]: Bit [6] Bit [7] 4 Src Port Select 0 Source port to be mirrored. Use illegal port number to disable mirroring 1 - select ingress data 0 - select egress data Reserved Reserved must be set to '1' 78 Zarlink Semiconductor Inc. Data Sheet 13.9.4 MIRROR2_DEST - Port Mirror destination CPU Address 703 Accessed by serial interface (R/W) (Default 00) 7 5 4 Dest Port Select Bit [4:0]: 0 ZL50417 Port Mirror Destination When port mirroring is enable, destination port can not serve as a data port. 13.10 13.10.1 (Group F Address) CPU Access Group GCR-Global Control Register CPU Address: hF00 Accessed by serial interface. (R/W) 7 4 3 Reset Bit [0]: Bit[1]: Bit[2]: 2 Bist 1 SR 0 SC Store configuration (Default = 0) Write `1' followed by `0' to store configuration into external EEPROM Store configuration and reset (Default = 0) Write `1' to store configuration into external EEPROM and reset chip Start BIST (Default = 0) Write `1' followed by `0' to start the device's built-in self-test. The result is found in the DCR register. Soft Reset (Default = 0) Write `1' to reset chip Reserved Bit[3]: Bit[7:4]: 13.10.2 DCR-Device Status and Signature Register CPU Address: hF01 Accessed by serial interface. (RO) 7 Revision Bit [0]: Bit[1]: 6 5 Signature 4 RE 3 2 BinP 1 BR BW 0 1: Busy writing configuration to IC 0: Not busy (not writing configuration to IC) 1: Busy reading configuration from IC 0: Not busy (not reading configuration from IC) Zarlink Semiconductor Inc. 79 ZL50417 Bit[2]: Bit[3]: Bit[5:4]: Bit [7:6]: 1: BIST in progress 0: BIST not running 1: RAM Error 0: RAM OK Device Signature 11: ZL50417 device Revision 00: Initial Silicon 01: XA1 Silicon 10: Production Silicon Data Sheet 13.10.3 DCR1-Giga port status CPU Address: hF02 Accessed by serial interface. (RO) 7 CIC Bit [1:0]: Giga port 0 strap option - 00 - 100Mb MII mode Bit[3:2] 01 - Reserved 10 - GMII 11 - PCS 6 4 3 GIGA1 2 1 GIGA0 0 Giga port 1 strap option - 00 - 100Mb MII mode 01 - Reserved 10 - GMII 11 - PCS Bit [7] Chip initialization completed 13.10.4 DPST - Device Port Status Register CPU Address:hF03 Accessed by serial interface (R/W) Bit[4:0]: Read back index register. This is used for selecting what to read back from DTST. (Default 00) 5'b00000 - Port 0 Operating mode and Negotiation status 5'b00001 - Port 1 Operating mode and Negotiation status 5'b00010 - Port 2 Operating mode and Negotiation status 5'b00011 - Port 3 Operating mode and Negotiation status 80 Zarlink Semiconductor Inc. Data Sheet 5'b00100 - Port 4 Operating mode and Negotiation status 5'b00101 - Port 5 Operating mode and Negotiation status 5'b00110 - Port 6 Operating mode and Negotiation status 5'b00111 - Port 7 Operating mode and Negotiation status 5'b01000 - Port 8 Operating mode and Negotiation status 5'b01001 - Port 9 Operating mode and Negotiation status 5'b01010 - Port 10 Operating mode and Negotiation status 5'b01011 - Port 11 Operating mode and Negotiation status 5'b01100 - Port 12 Operating mode and Negotiation status 5'b01101 - Port 13 Operating mode and Negotiation status 5'b01110 - Port 14 Operating mode and Negotiation status 5'b01111 - Port 15 Operating mode and Negotiation status 5'b10000 - Reserved 5'b10001 - Reserved 5'b10010 - Reserved 5'b00011 - Reserved 5'b10100 - Reserved 5'b10101 - Reserved 5'b10110 - Reserved 5'b10111 - Reserved 5'b11000 - Reserved 5'b11001 - Port 25 Operating mode/Neg status (Gigabit 1) 5'b11010 - Port 26 Operating mode/Neg status (Gigabit 2) ZL50417 13.10.5 DTST - Data read back register CPU Address: hF04 Accessed by serial interface (RO) This register provides various internal information as selected in DPST bit[4:0]. Refer to the PHY Control Application Note. 7 MD 6 5 Sig 4 Giga 3 Inkdn 2 FE 1 Fdpx 0 FcEn Zarlink Semiconductor Inc. 81 ZL50417 When bit is 1: Bit[0] - Flow control enable Bit[1] - Full duplex port Bit[2] - Fast Ethernet port (if not gigabit port) Bit[3] - Link is down Bit[4] - Giga port Bit[5] - Signal detect (when PCS interface mode) Bit[6] - reserved Bit[7] - Module detected (for hot swap purpose) Data Sheet 13.10.6 PLLCR - PLL Control Register CPU Address: hF05 Accessed by serial interface (RW) Bit[3] - Must be '1' Bit[7] - Selects strap option or LCLK/OECLK registers 0 - Strap option (default) 1 - LCLK/OECLK registers 13.10.7 LCLK - LA_CLK delay from internal OE_CLK CPU Address: hF06 Accessed by serial interface (RW) PD[12:10] 000b 001b 010b 011b 100b 101b 110b 111b LCLK 80h 40h 20h 10h 08h 04h 02h 01h Delay 8 Buffers Delay 7 Buffers Delay 6 Buffers Delay 5 Buffers Delay (Recommend) 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register. 82 Zarlink Semiconductor Inc. Data Sheet 13.10.8 OECLK - Internal OE_CLK delay from SCLK CPU Address: hF07 Accessed by serial interface (RW) The OE_CLK is used for generating the OE0 and OE1 signals. ZL50417 PD[15:13] 000b 001b 010b 011b 100b 101b 110b 111b OECLK Delay 80h 40h 20h 10h 08h 04h 02h 01h 8 Buffers Delay 7 Buffers Delay (Recommend) 6 Buffers Delay 5 Buffers Delay 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay 13.10.9 DA - DA Register CPU Address: hFFF Accessed by serial interface (RO) Always return 8'h DA. Indicate the serial port connection is good. 13.11 TBI Registers Two sets of TBI registers are used for configure the two Gigabit ports if they are operating in TBI mode. These TBI registers are located inside the switching chip and they are accessed through the MII command and MII data registers. 13.11.1 Control Register MII Address: h00 Read/Write Bit [15] Reset PCS logic and all TBI registers 1 = Reset. 0 = Normal operation. Reserved. Must be programmed with "0". Speed selection (See bit 6 for complete details) Auto Negotiation Enable 1 = Enable auto-negotiation process. 0 = Disable auto-negotiation process (Default). Reserved. Must be programmed with "0" Bit [14] Bit [13] Bit [12] Bit [11:10] Zarlink Semiconductor Inc. 83 ZL50417 Bit [9] Restart Auto Negotiation. 1 = Restart auto-negotiation process. 0 = Normal operation (Default). Reserved. Speed Selection Bit[6][13] 1 1 = Reserved 0 =1000Mb/s (Default) 1 =100Mb/s 0 0 =10Mb/s Reserved. Must be programmed with "0". Data Sheet Bit [8:7] Bit [6] Bit [5:0] 13.11.2 Status Register MII Address: h01 Read Only Bit [15:9] Bit [8] Bit [7:6] Bit [5] Reserved. Always read back as "0". Reserved. Always read back as "1". Reserved. Always read back as "0". Auto-Negotiation Complete 1 = Auto-negotiation process completed. 0 = Auto-negotiation process not completed. Reserved. Always read back as "0" Reserved. Always read back as "1" Link Status 1 = Link is up. 0 = Link is down. Reserved. Always read back as "0". Reserved. Always read back as "1". Bit [4] Bit [3] Bit [2] Bit [1] Bit [0] 84 Zarlink Semiconductor Inc. Data Sheet 13.11.3 Advertisement Register MII Address: h04 Read/Write Bit [15] Next Page 1 = Has next page capabilities. 0 = Do not has next page capabilities (Default). Reserved. Always read back as "0". Read Only. Remote Fault. Default is "0". Reserved. Always read back as "0". Read Only. Pause. Default is "00" Half Duplex 1 = Support half duplex (Default). 0 = Do not support half duplex. Full duplex 1 = Support full duplex (Default). 0 = Do not support full duplex. Reserved. Always read back as "0". Read Only. ZL50417 Bit [14] Bit [13:12] Bit [11:9] Bit [8:7] Bit [6] Bit [5] Bit [4:0] 13.11.4 Link Partner Ability Register MII Address: h05 Read Only Bit [15] Next Page 1 = Has next page capabilities. 0 = Do not has next page capabilities. Acknowledge Remote Fault. Reserved. Always read back as "0". Pause. Half Duplex 1 = Support half duplex. 0 = Do not support half duplex. Full duplex 1 = Support full duplex. 0 = Do not support full duplex. Reserved. Always read back as "0". Bit [14] Bit [13:12] Bit [11:9] Bit [8:7] Bit [6] Bit [5] Bit [4:0] Zarlink Semiconductor Inc. 85 ZL50417 13.11.5 Expansion Register Data Sheet MII Address: h06 Read Only Bit [15:2] Bit [1] Reserved. Always read back as "0". Page Received. 1 = A new page has been received. 0 = A new page has not been received. Reserved. Always read back as "0". Bit [0] 13.11.6 Extended Status Register MII Address: h15 Read Only Bit [15] 1000 Full Duplex 1 = Support 1000 full duplex operation (Default). 0 = Do not support 1000 full duplex operation. 1000 Half Duplex 1 = Support 1000 half duplex operation (Default). 0 = Do not support 1000 half duplex operation. Reserved. Always read back as "0". Bit [14] Bit [13:0] 86 Zarlink Semiconductor Inc. Data Sheet 14.0 14.1 1 A B C D E 2 ZL50417 BGA and Ball Signal Descriptions BGA Views (TOP-View) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D LA_D OE_ LA_ TRUN RESE RESE SCL 4 7 10 13 15 4 E0_ 8 13 16 19 33 36 39 42 45 C L K 0 C L K 0 K 1 RV E D RV E D SDA STRO TSTO BE UT7 D0 TSTO TSTO UT8 UT3 LA_D LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D LA_D OE_ LA_ LA_D RESE RESE TRUN RESE 1 3 6 9 12 14 DSC_ E1_ 7 12 15 18 32 35 38 41 44 CLK1 CLK1 6 2 RV E D RV E D K 2 RV E D LA_C LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_W T_MO LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D OE_ LA_ LK 0 2 5 8 11 3 E_ E_ DE1 11 14 17 20 34 37 40 43 CLK2 CLK2 P_D TRUN RESE RESE AUTO TSTO TSTO TSTO TSTO K 0 RV E D RV E D F D U T 1 1 U T 9 U T 4 U T 0 AGN LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_A LA_A LA_W LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D SCAN SCAN TSTO TSTO TSTO TSTO TSTO TSTO D 17 19 21 23 25 27 29 31 6 10 E0_ 49 51 53 55 57 59 61 63 47 COL CLK UT14 UT13 UT12 UT10 UT5 UT1 SCLK LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_A LA_A LA_W LA_D LA_D LA_D LA_D LA_D LA_D LA_D RESE LA_D 16 18 20 22 24 26 28 30 5 9 E1_ 48 50 52 54 56 58 60 RV E D 46 AV C C R E S I S C A N L B _ D L B _ D N_ EN 63 62 LB_C RESE LB_D LB_D LB_D LK TOUT 47 61 60 LB_D LB_D LB_D LB_D LB_D 46 45 44 59 58 LB_D LB_D LB_D LB_D LB_D 43 42 41 57 56 LB_D LB_D LB_D LB_D LB_D 40 39 38 55 54 LB_D LB_D LB_D LB_D LB_D 37 36 35 53 52 LB_D LB_D LB_D LB_D LB_D 34 33 32 51 50 LB_A LB_A LB_A LB_D LB_D VCC 18 19 20 49 48 LB_A LB_A LB_A LB_W LB_W VCC 15 16 17 E0_ E1_ LB_A LB_A LB_A LB_A LB_A VCC 10 11 12 13 14 LB_A LB_A LB_A LB_A LB_A VCC 5 6 7 8 9 LB_O LB_O T_MO LB_D LB_D VCC E0_ E1_ DE0 31 30 LB_A LB_O LB_W LB_D LB_D DSC_ E_ E_ 29 28 LB_D LB_A LB_A LB_D LB_D 15 3 4 27 26 LB_D LB_D LB_D LB_D LB_D 14 13 12 25 24 VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VCC VCC VCC VCC VCC SCAN TSTO M26_ M26_ SCAN TSTO TSTO LINK UT15 CRS TXER MOD UT6 UT2 M26_ M26_ M26_ M26_ M26_ T X C L T X E N M T X - RXDV R X C L RESE RESE RESE M26_ M26_ RV E D RV E D RV E D R X E R C O L RESE RESE RESE RESE RESE RV E D RV E D RV E D RV E D R V E D RESE RESE M26_ RESE RESE RV E D RV E D R X D 9 RV E D R V E D M26_ M26_ M26_ M26_ M26_ TXD9 TXD8 RXD6 RXD7 RXD8 M26_ M26_ M26_ M26_ M26_ TXD4 TXD6 RXD3 RXD4 RXD5 M26_ M26_ M26_ M26_ M26_ TXD7 TXD5 RXD0 RXD1 RXD2 VCC M26_ M26_ TXD2 TXD3 VCC M26_ M26_ TXD0 TXD1 VCC M25_ M25_ CRS TXER GREF _CLK MDIO GREF _CLK MDC M_CL K F G H J K L M N P VSS VSS VSS VSS VSS VSS VSS R T VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC M25_ M25_ M25_ M25_ M25_ T X C L T X E N M T X - RXDV R X C L VDD VDD VCC RESE RESE RESE M25_ M25_ RV E D RV E D RV E D R X E R C O L RESE RESE RESE RESE RESE RV E D RV E D RV E D RV E D R V E D RESE RESE M25_ RESE RESE RV E D RV E D R X D 9 RV E D R V E D M25_ M25_ M25_ M25_ M25_ RXD6 TXD8 TXD9 RXD7 RXD8 M25_ M25_ M25_ M25_ M25_ TXD6 TXD7 RXD3 RXD4 RXD5 M25_ M25_ M25_ M25_ M25_ TXD4 TXD5 RXD0 RXD1 RXD2 M25_ M25_ RESE RESE RESE T X D 2 T X D 3 RV E D RV E D R V E D U V W Y VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AA LB_D LB_D LB_D LB_D LB_D 11 10 9 23 22 AB LB_D LB_D LB_D LB_D LB_D 8 7 6 21 20 AC LB_D LB_D LB_D LB_D LB_D 5 4 3 19 18 AD LB_D LB_D LB_D LB_D LB_D 2 1 0 17 16 VCC VCC VCC VCC VCC M25_ M25_ RESE RESE RESE T X D 0 T X D 1 RV E D RV E D R V E D AE M0_T M0_T M0_T M3_T M3_T M3_R M5_T M5_T M5_R M8_T M8_T M8_R M10_ M10_ M10_ M13_ RESE M15_ RESE M15_ M15_ RESE RESE RESE RESE RESE RESE RESE X E N X D 0 X D 1 X D 1 X E N X D 0 X D 1 X E N X D 0 X D 1 X E N X D 0 T X D 1 T X E N R X D 0 T X D 1 RV E D T X D 1 RV E D T X E N R X D 0 RV E D RV E D RV E D RV E D RV E D RV E D RV E D AF M0_R M0_R M0_C M3_T M3_C M3_R M5_T M5_C M5_R M8_T M8_C M8_R M10_ M10_ M10_ M13_ M13_ M13_ M14_ RESE M15_ RESE RESE RESE RESE RESE RESE RESE RESE XD1 XD0 RS XD0 RS XD1 XD0 RS XD1 XD0 RS X D 1 T X D 0 C R S R X D 1 T X D 0 C R S R X D 1 C R S R V E D R X D 1 RV E D RV E D RV E D RV E D RV E D RV E D RV E D R V E D A G M 1 _T M1 _T M1 _T M2 _T M2 _C M4 _T M4 _C M6 _T M6 _C M7_ T M7_ C M9_ T M9_ C M11_ M11_ M12 _ M12 _ M14 _ M15 _ RE SE R E SE R E SE R E SE R E SE R E SE R E SE R E SE R E SE R ES E XEN XD0 XD1 XD1 RS XD1 RS XD1 RS XD1 RS XD1 R S T X D 1 C R S T X D 1 C R S T X D 1 T X D 0 R V E D RV E D RV E D RV E D RV E D RV E D RV E D RV E D RV E D R V E D AH AJ M 1 _R M1 _C M2 _T M2 _R M4 _T M4 _R M6 _T M6 _R M7_ T M7_ R M9_ T M9_ R M11_ M11_ M12 _ M12 _ M14 _ M14 _ M13 _ M1 5_ R E SE R E SE R E SE R E SE R E SE R E SE R E SE XD0 RS X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 T X D 0 R X D 0 T X D 0 R X D 0 T X D 0 R X D 0 R X D 0 C R S RV E D RV E D RV E D RV E D RV E D RV E D RV E D M 1 _R M2 _T M2 _R M4 _T M4 _R M6 _T M6 _R M7_ T M7_ R M9_ T M9_ R M11_ M11_ M12 _ M12 _ M14 _ M14 _ RE SE M1 3_ R E SE R E SE R E SE R E SE R E SE R E SE X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 T X E N R X D 1 T X E N R X D 1 T X E N R X D 1 R V E D T X E N RV E D RV E D RV E D RV E D RV E D RV E D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Zarlink Semiconductor Inc. 87 ZL50417 14.2 Power and Ground Distribution Data Sheet The following figure provides an encapsulated view of the power and ground distribution. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDA 26 27 28 29 L A_D LA_D LA _D LA _D L A_D LA_A LA _O LA _A L A_A LA_A LA _A LA _D LA _D LA_D LA_D LA _D RE SE RE SE T RUN MI RR M IRR SCL 4 7 10 13 15 4 E0_ 8 13 16 19 33 36 39 42 45 RVED RVED K1 OR4 OR1 ST RO T STO BE UT7 D0 TSTO TSTO UT 8 UT 3 LA _D L A_D LA_D LA _D LA _D L A_D LA_A LA _O LA _A L A_A LA_A LA _A LA _D LA _D LA_D LA_D LA _D RE SE RE SE LA_D MI RR M IRR T RUN RE SE 1 3 6 9 12 14 DSC_ E1_ 7 12 15 18 32 35 38 41 44 RVED RVED 62 OR5 OR2 K2 RVED LA _C LA _D L A_D LA_D LA _D LA _D L A_A LA_O LA_ W T_ MO L A_A LA_A LA _A LA _A LA _D LA_D LA_D LA _D RE SE RE SE RE SE T RUN M IRR M I RR A UT O T ST O T STO T STO T STO LK 0 2 5 8 11 3 E_ E_ DE1 11 14 17 20 34 37 40 43 RVED RVED RVED K0 OR3 OR0 FD UT 11 UT 9 UT 4 UT 0 A GN LA _D L A_D LA_D LA _D LA _D L A_D LA_D LA _D LA _A L A_A L A_ W LA _D LA _D LA _D LA_D LA_D LA _D LA _D LA_D LA_D S C AN SC AN T STO T STO T ST O T STO T STO T STO D 17 19 21 23 25 27 29 31 6 10 E0_ 49 51 53 55 57 59 61 63 47 C OL C LK UT 14 UT 13 UT 12 UT 10 UT 5 UT 1 S CL K LA _D L A_D LA_D LA _D LA _D L A_D LA_D LA _D LA _A L A_A L A_ W LA _D LA _D LA _D LA_D LA_D LA _D LA _D RE SE LA_D 16 18 20 22 24 26 28 30 5 9 E1_ 48 50 52 54 56 58 60 RVED 46 A VC C RE SI SC AN LB_D LB_ D N_ EN 63 62 VCC VCC VCC VCC VCC S C AN SC AN T STO M 26_ M 26 _ MOD LI NK UT 15 C RS T XE R E M26_ M26_ M26_ TXCL MTX TXEN CLK K TSTO TSTO UT 6 UT 2 M26_ M26_ RXD RXCL V K RESE LB_D LB_D LB_D LB_C T OUT 47 61 60 LK _ LB_D LB_D LB_D LB_D LB_D 46 45 44 59 58 LB_D LB_D LB_D LB_D LB_D 43 42 41 57 56 LB_D LB_D LB_D LB_D LB_D 40 39 38 55 54 LB_D LB_D LB_D LB_D LB_D 37 36 35 53 52 LB_D LB_D LB_D LB_D LB_D 34 33 32 51 50 LB_A LB_A LB_A LB_D LB_D VCC 18 19 20 49 48 LB_A LB_A LB_A LB_W LB_ VCC 15 16 17 E0_ WE1_ LB_A LB_A LB_A LB_A LB_A VCC 10 11 12 13 14 LB_A LB_A LB_A LB_A LB_A VCC 5 6 7 8 9 LB_O LB_O T_MO LB_D LB_D VCC E0_ E1_ DE0 31 30 LB_A LB_O LB_W LB_D LB_D DSC_ E_ E_ 29 28 LB_D LB_A LB_A LB_D LB_D 15 3 4 27 26 LB_D LB_D LB_D LB_D LB_D 14 13 12 25 24 LB_D LB_D LB_D LB_D LB_D 11 10 9 23 22 LB_D LB_D LB_D LB_D LB_D 8 7 6 21 20 LB_D LB_D LB_D LB_D LB_D 5 4 3 19 18 LB_D LB_D LB_D LB_D LB_D 2 1 0 17 16 VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD RE SE RE SE RE SE M26 _ M 26_ RVED RVED RVED RXER COL RE SE RE SE RE SE RE SE RE SE RVED RVED RVED RVED RVED RE SE RE SE M26 _ RE SE RE SE RVED RVED RXD9 RVED RVED M26_ M26_ M26_ M26_ M26_ T XD9 T XD8 RX D6 RXD7 RXD 8 M26_ M26_ M26_ M26_ M26_ T XD4 T XD6 RX D3 RXD4 RXD 5 M26_ M26_ M26_ M26_ M26_ T XD7 T XD5 RX D0 RXD1 RXD 2 D_CO D_CO GREF V CC M26 _ M 26 _ N FIG NF IG _ C LK T XD2 T XD3 1 0 1 GREF VCC M26_ M26_ MD IO _ C LK T XD0 T XD1 0 VCC M25_ M25_ CRS TXER MDC M_CL K VDD VSS VSS VSS VSS VSS VSS VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS M25_ M25_ M25_ M25_ M25_ V CC T XC L T XEN M TX RX D RXC L K CLK V K VDD VCC RESE RE SE RE SE M25 _ M 25_ RVE RVED RVED RXER COL D RE SE RE SE RE SE RE SE RE SE RVED RVED RVED RVED RVED RE SE RE SE M25 _ RE SE RE SE RVED RVED RXD9 RVED RVED M25_ M25_ M25_ M25_ M25_ RXD 6 T XD8 T XD9 RXD7 RXD 8 M25_ M25_ M25_ M25_ M25_ T XD6 T XD7 RX D3 RXD4 RXD 5 M25_ M25_ M25_ M25_ M25_ T XD4 T XD5 RX D0 RXD1 RXD 2 M 25_ M 25 _ RE SE RE SE RE SE T XD2 T XD3 RVED RVED RV ED M 25_ M 25 _ RE SE RE SE RE SE T XD0 T XD1 RVED RVED RV ED VSS VSS VSS VSS VSS VSS VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD M0_T M 0_T M 0_T M3_T M3_T M 3_R M 5_T M 5_T M 5_ R M8_T M 8_T M8_ R M 10 _ M10 _ M10 _ M 13_ RE SE M15 _ RE SE M 15_ M 15_ RE SE RE SE RE SE RE SE RE SE RE SE RE SE X EN XD 0 X D1 X D1 X EN XD 0 X D1 XEN XD 0 XD 1 X EN X D0 T XD1 T XEN RXD0 T XD1 RV ED T XD1 RVED T XEN RXD 0 RV ED RVED RVE D RV ED RV ED RVED RVE D M 0_R M 0_R M0_ C M3_T M 3_ C M 3_R M 5_T M5_ C M 5_ R M8_T M 8_ C M8_ R M 10 _ M10 _ M10 _ M 13_ M 13 _ M13 _ M14 _ RE SE M 15_ RE SE RE SE RE SE RE SE RE SE RE SE RE SE RE SE F XD1 XD0 RS XD0 RS XD1 XD0 RS XD1 XD0 RS X D1 T XD0 CRS RXD1 T XD0 C RS RX D1 C RS RV ED RXD 1 RV ED RVED RVE D RV ED RV ED RVED RVE D RV ED M1_T M 1_T M 1_T M2_T M 2_ C M 4_T M4_ C M 6_T M 6_ C M7_T M 7_ C M 9_T M9_ C M11 _ M11 _ M 12_ M 12 _ M14 _ M15 _ RE SE RE SE RE SE RE SE RE SE RE SE RE SE RE SE RE SE RE SE XEN XD0 XD1 XD1 RS XD1 RS XD1 RS XD1 RS XD1 RS T XD1 C RS T XD1 C RS T XD1 T XD0 RV ED RV ED RV ED RVED RVE D RV ED RV ED RVED RVE D RV ED M 1_R M1_ C M2_T M 2_ R M 4_T M4_ R M 6_T M 6_ R M7_T M 7_ R M 9_T M9_ R M11 _ M11 _ M 12_ M 12 _ M14 _ M14 _ M 13_ M 15_ RE SE RE SE RE SE RE SE RE SE RE SE RE SE XD0 RS X D0 XD 0 XD 0 X D0 X D0 XD 0 XD 0 X D0 X D0 XD 0 T XD0 RXD0 T XD0 RX D0 T XD0 RX D0 RXD 0 C RS RV ED RVED RVE D RV ED RV ED RVED RVE D J 1 2 M1_ R M2_T M 2_ R M 4_T M4_ R M 6_T M 6_ R M7_T M 7_ R M 9_T M9_ R M11 _ M11 _ M 12_ M 12 _ M14 _ M14 _ RE SE M 13_ RE SE RE SE RE SE RE SE RE SE RE SE X D1 XEN XD 1 X EN X D1 XEN XD 1 X EN X D1 XEN XD 1 T XEN RXD1 T XEN RX D1 T XEN RX D1 RV ED T XEN RV ED RVED RVE D RV ED RV ED RVED 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 88 Zarlink Semiconductor Inc. Data Sheet 14.2.1 Ball Signal Descriptions Ball No(s) Symbol I/O ZL50417 Description IC Interface Note: Use IC and Serial control interface to configure the system A24 A25 Serial Control Interface A26 B26 C25 Frame Buffer Interface D20, B21, D19, E19,D18, E18, D17, E17, D16, E16, D15, E15, D14, E14, D13, E13, D21, E21, A18, B18, C18, A17, B17, C17, A16, B16, C16, A15, B15, C15, A14, B14, D9, E9, D8, E8, D7, E7, D6, E6, D5, E5, D4, E4, D3, E3, D2, E2, A7, B7, A6, B6, C6, A5, B5, C5, A4, B4, C4, A3, B3, C3, B2, C2 C14, A13, B13, C13, A12, B12, C12, A11, B11, C11, D11, E11, A10, B10, D10, E10, A8, C7 B8 C1 C9 LA_D[63:0] I/O-TS with pull up Frame Bank A- Data Bit [63:0] STROBE D0 AUTOFD Input with weak internal pull up Input with weak internal pull up Output with pull up Serial Strobe Pin Serial Data Input Serial Data Output (AutoFD) SCL SDA Output I/O-TS with internal pull up IC Data Clock IC Data I/O LA_A[20:3] Output Frame Bank A - Address Bit [20:3] LA_ADSC# LA_CLK LA_WE# Output with pull up Output with pull up Output with pull up Frame Bank A Address Status Control Frame Bank A Clock Input Frame Bank A Write Chip Select for one layer SRAM application Frame Bank A Write Chip Select for lower layer of two bank SRAM application Frame Bank A Write Chip Select for upper bank of two layer SRAM application D12 LA_WE0# Output with pull up E12 LA_WE1# Output with pull up Zarlink Semiconductor Inc. 89 ZL50417 Ball No(s) C8 Symbol LA_OE# I/O Output with pull up Data Sheet Description Frame Bank A Read Chip Select for one layer SRAM application Frame Bank A Read Chip Select for lower layer of two layers SRAM application Frame Bank A Read Chip Select for upper layer of two layers SRAM application Frame Bank B- Data Bit [63:0] A9 LA_OE0# Output with pull up B9 LA_OE1# Output with pull up F4, F5, G4, G5, H4, H5, J4, J5, K4, K5, L4, L5, M4, M5, N4, N5, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, M1, M2, M3, U4, U5, V4, V5, W4, W5, Y4, Y5, AA4, AA5, AB4, AB5, AC4, AC5, AD4, AD5, W1, Y1, Y2, Y3, AA1, AA2, AA3, AB1, AB2, AB3, AC1, AC2, AC3, AD1, AD2, AD3 N3, N2, N1, P3, P2, P1, R5, R4, R3, R2, R1, T5, T4, T3, T2, T1, W3, W2 V1 G1 V3 LB_D[63:0] I/O-TS with pull up. LB_A[20:3] Output Frame Bank B - Address Bit [20:3] Frame Bank B Address Status Control Frame Bank B Clock Input Frame Bank B Write Chip Select for one layer SRAM application Frame Bank B Write Chip Select for lower layer of two layers SRAM application Frame Bank B Write Chip Select for upper layer of two layers SRAM application Frame Bank B Read Chip Select for one layer SRAM application Frame Bank B Read Chip Select for lower layer of two layers SRAM application Frame Bank B Read Chip Select for upper layer of two layers SRAM application LB_ADSC# LB_CLK LB_WE# Output with pull up Output with pull up Output with pull up P4 LB_WE0# Output with pull up P5 LB_WE1# Output with pull up V2 LB_OE# Output with pull up U1 LB_OE0# Output with pull up U2 LB_OE1# Output with pull up 90 Zarlink Semiconductor Inc. Data Sheet Ball No(s) Symbol I/O ZL50417 Description Fast Ethernet Access Ports [15:0] RMII R28 M_MDC Output MII Management Data Clock - (Common for all MII Ports [15:0]) MII Management Data I/O - (Common for all MII Ports - [15:0]) Reference Input Clock Ports [15:0] - Receive Data Bit [1] P28 M_MDIO I/O-TS with pull up R29 AF21, AJ19, AF18, AJ17, AJ15, AF15, AJ13, AF12, AJ11, AJ9, AF9, AJ7, AF6, AJ5, AJ3, AF1 AE21, AH19, AH20, AH17, AH15, AE15, AH13, AE12, AH11, AH9, AE9, AH7, AE6, AH5, AH2, AF2 AH21, AF19, AF17, AG17, AG15, AF14, AG13, AF11, AG11, AG9, AF8, AG7, AF5, AG5, AH3, AF3 AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1 AE18, AG18, AE16, AG16, AG14, AE13, AG12, AE10, AG10, AG8, AE7, AG6, AE4, AG4, AG3, AE3 AG19, AH18, AF16, AH16, AH14, AF13, AH12, AF10, AH10, AH8, AF7, AH6, AF4, AH4, AG2, AE2 M_CLKI M[15:0]_RXD[1] Input Input with weak internal pull up resistors. M[15:0]_RXD[0] Input with weak internal pull up resistors Ports [15:0] - Receive Data Bit [0] M[15:0]_CRS_DV Input with weak internal pull down resistors. Ports [15:0] - Carrier Sense and Receive Data Valid M[15:0]_TXEN I/O- TS with pull up, slew Ports [15:0] - Transmit Enable Strap option for RMII/GPSI M[15:0]_TXD[1] Output, slew Ports [15:0] - Transmit Data Bit [1] M[15:0]_TXD[0] Output, slew Ports [15:0] - Transmit Data Bit [0] GMII/TBI GiGabit Ethernet Access Ports 0 & 1 Y27, Y26, AA26, AA25, AB26, AB25, AC26, AC25, AD26, AD25 T28 U28 R25 M25_TXD[9:0] Output Transmit Data Bit [9:0] M25_RX_DV M25_RX_ER M25_CRS Input w/ pulldown Input w/ pullup Input w/ pulldown Receive Data Valid Receive Error Carrier Sense Zarlink Semiconductor Inc. 91 ZL50417 Ball No(s) U29 T29 W27, Y29, Y28, Y25, AA29, AA28, AA27, AB29, AB28, AB27 T26 R26 T25 P29 K25, K26, M25, L26, M26, L25, N26, N25, P26, P25 F28 G28 E25 G29 F29 J27, K29, K28, K27, L29, L28, L27, M29, M28, M27 F26 E26 F25 N29 LED Interface C29 D29 E29 B28 C28 D28 E28 LED_CLK/TSTOUT0 LED_SYN/TSTOUT1 LED_BIT/TSTOUT2 G1_RXTX#/TSTOUT3 G1_DPCOL#/TSTOUT4 G1_LINK#/TSTOUT5 G2_RXTX#/TSTOUT6 I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up Symbol M25_COL M25_RXCLK M25_RXD[9:0] I/O Input w/ pullup Input w/ pullup Input w/ pullup Data Sheet Description Collision Detected Receive Clock Receive Data Bit [9:0] M25_TX_EN M25_TX_ER M25_ TXCLK GREF_CLK0 M26_TXD[9:0] Output w/ pullup Output w/ pullup Output Input w/ pullup Output Transmit Data Enable Transmit Error Gigabit Transmit Clock Gigabit Reference Clock Transmit Data Bit [9:0] M26_RX_DV M26_RX_ER M26_CRS M26_COL M26_RXCLK M26_RXD[9:0] Input w/ pulldown Input w/ pullup Input w/ pulldown Input w/ pullup Input w/ pullup Input w/ pullup Receive Data Valid Receive Error Carrier Sense Collision Detected Receive Clock Receive Data Bit [9:0] M26_TX_EN M26_TX_ER M26_ TXCLK GREF_CLK1 Output w/ pullup Output w/ pullup Output Input w/ pullup Transmit Data Enable Transmit Error Gigabit Transmit Clock Gigabit Reference Clock LED Serial Interface Output Clock LED Output Data Stream Envelope LED Serial Data Output Stream LED for Gigabit port 1 (receive + transmit) LED for Gigabit port 1 (full duplex + collision) LED for Gigabit port 1 LED for Gigabit port 2 (receive + transmit) 92 Zarlink Semiconductor Inc. Data Sheet Ball No(s) A27 B27 C27 D27 C26 D26 D25 D24 E24 Trunk Enable C22 TRUNK0 Input w/ weak internal pull down resistors Symbol G2_DPCOL#/TSTOUT7 G2_LINK#/TSTOUT8 INIT_DONE/TSTOUT9 INIT_START/TSTOUT1 0 CHECKSUM_OK/TSTO UT11 FCB_ERR/TSTOUT12 MCT_ERR/TSTOUT13 BIST_IN_PRC/TSTOUT 14 BIST_DONE/TSTOUT1 5 I/O I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up ZL50417 Description LED for Gigabit port 2 (full duplex + collision) LED for Gigabit port 2 System start operation Start initialization EEPROM read OK FCB memory self test fail MCT memory self test fail Processing memory self test Memory self test done Trunk Port Enable in unmanaged mode In managed mode doesn't care Trunk Port Enable in unmanaged mode In managed mode doesn't care Trunk Port Enable in unmanaged mode In managed mode doesn't care A21 TRUNK1 Input w/ weak internal pull down resistors B24 TRUNK2 Input w/ weak internal pull down resistors Test Facility U3, C10 T_MODE0, T_MODE1 I/O-TS Test Pins 00 - Test mode - Set Mode upon Reset, and provides NAND Tree test output during test mode 01 - Reserved - Do not use 10 - Reserved - Do not use 11 - Normal mode. Use external pull up for normal mode Scan Enable 0 - Normal mode (open) 1 - Enable Test mode 0 - Normal mode (open) F3 E27 SCAN_EN SCANMODE Input with pull down Input with pull down System Clock, Power, and Ground Pins Zarlink Semiconductor Inc. 93 ZL50417 Ball No(s) E1 K12, K13, K17,K18 M10, N10, M20, N20, U10, V10, U20, V20, Y12, Y13, Y17, Y18 F13, F14, F15, F16, F17, N6, P6, R6, T6, U6, N24, P24, R24, T24, U24, AD13, AD14, AD15, AD16, AD17 M12, M13, M14, M15, M16, M17, M18, N12, N13, N14, N15, N16, N17, N18, P12, P13, P14, P15, P16, P17, P18, R12, R13, R14, R15, R16, R17, R18, T12, T13, T14, T15, T16, T17, T18, U12, U13, U14, U15, U16, U17, U18, V12, V13, V14, V15, V16, V17, V18, F1 D1 MISC D22 D23 E23 F2 G2 SCANCOL SCANCLK SCANLINK RESIN# RESETOUT_ Input Input/ output Input Input Output SCLK VDD Symbol Input Power I/O Data Sheet Description System Clock at 100 MHz +2.5 Volt DC Supply VCC Power +3.3 Volt DC Supply VSS Power Ground Ground AVCC AGND Analog Power Analog Ground Analog +2.5 Volt DC Supply Analog Ground Scans the Collision signal of Home PHY Clock for scanning Home PHY collision and link Link up signal from Home PHY Reset Input Reset PHY 94 Zarlink Semiconductor Inc. Data Sheet Ball No(s) AC29, AE28, AJ27, AF27, AJ25, AF24, AH23, AE19, AC27, AF29, AG27, AF26, AG25, AG23, AF23, AG21, AC28, AF28, AH27, AE27, AH25, AE24, AF22, AF20, AD29, AG28, AJ26, AE26, AJ24, AE23, AJ22, AJ20, AD27, AH28, AG26, AE25, AG24, AE22, AJ23, AG20, AD28, AG29, AH26, AF25, AH24, AG22, AH22, AE17, G27, H29, H28, H27, J29, J28, U26, U25, V26, V25, W26, W25, G26, G25, H26, H25, J26, J25, U27, V29, V28, V27, W29, W28, B22, A22, C23, B23, A23, C24, E20, B25 Symbol RESERVED NA I/O ZL50417 Description Reserved Pins. Leave unconnected. Bootstrap Pins (Default = pull up, 1= pull up 0= pull down) After reset TSTOUT0 to TSTOU15 are used by the LED interface. C29 TSTOUT0 Default 1 GIGA Link polarity 0 - active low 1 - active high RMII MAC Power Saving Enable 0 - No power saving 1 - power saving Giga Half Duplex Support 0 - Disable 1 - Enable Module detect enable 0 - Hot swap enable 1 - Hot swap disable Reserved Default 1 Scan Speed: 1/4 SCLK or SCLK 0 - 1/4 SCLK (HPNA) 1 - SCLK Reserved D29 TSTOUT1 Default 1 E29 TSTOUT2 Default 1 Recommend disable (0) with pull-down Default 1 B28 TSTOUT3 C28 D28 TSTOUT4 TSTOUT5 E28 TSTOUT6 Zarlink Semiconductor Inc. 95 ZL50417 Ball No(s) A27 Symbol TSTOUT7 Default 1 I/O Data Sheet Description Memory Size 0 - 256K x 32 or 256K x 64 (4M total) 1 - 128K x 32 or 128K x 64 (2M total) EEPROM Installed 0 - EEPROM installed 1 - EEPROM not installed MCT Aging 0 - MCT aging disable 1 - MCT aging enable FCB Aging 0 - FCB aging disable 1 - FCB aging enable Timeout Reset 0 - Time out reset disable 1 - Time out reset enable. Issue reset if any state machine did not go back to idle for 5sec. Reserved Default 1 FDB RAM depth (1 or 2 layers) 0 - 2 layer 1 - 1 layer Reserved Default 1 SRAM Test Mode 0 - Enable test mode 1 - Normal operation Giga0 Mode: G0_TXEN G0_TXER 0 0 1 1 0 1 0 1 MII RSVD GMII PCS B27 TSTOUT8 Default 1 C27 TSTOUT9 Default 1 D27 TSTOUT10 Default 1 C26 TSTOUT11 Default 1 D26 D25 TSTOUT12 TSTOUT13 D24 E24 TSTOUT14 TSTOUT15 T26, R26 G0_TXEN, G0_TXER Default: PCS F26, E26 G1_TXEN, G1_TXER Default: PCS Giga1 Mode: G1_TXEN G1_TXER 0 0 1 1 0 1 0 1 MII RSVD GMII PCS 96 Zarlink Semiconductor Inc. Data Sheet Ball No(s) AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1, C21 C19, B19, A19 Symbol M[15:0]_TXEN I/O Default: RMII ZL50417 Description 0 - GPSI 1 - RMII P_D OE_CLK[2:0] Must be pulled-down Default: 111 Reserved - Must be pulleddown Programmable delay for internal OE_CLK from SCLK input. The OE_CLK is used for generating the OE0 and OE1 signals. Suggested value is 011. Programmable delay for LA_CLK and LB_CLK from internal OE_CLK. The LA_CLK and LB_CLK delay from SCLK is the sum of the delay programmed in here and the delay in P_D[15:13]. Suggested value is 011. C20, B20, A20 LA_CLK[2:0] Default: 111 Notes: #= Input = In-ST = Output = Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) OutOD= I/O-TS = I/O-OD = Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver Zarlink Semiconductor Inc. 97 ZL50417 14.3 Ball Signal Name Data Sheet Ball No. D20 B21 D19 E19 D18 E18 D17 E17 D16 E16 D15 E15 D14 E14 D13 E13 D21 E21 A18 B18 C18 A17 B17 C17 A16 B16 C16 A15 B15 C15 Signal Name LA_D[63] LA_D[62] LA_D[61] LA_D[60] LA_D[59] LA_D[58] LA_D[57] LA_D[56] LA_D[55] LA_D[54] LA_D[53] LA_D[52] LA_D[51] LA_D[50] LA_D[49] LA_D[48] LA_D[47] LA_D[46] LA_D[45] LA_D[44] LA_D[43] LA_D[42] LA_D[41] LA_D[40] LA_D[39] LA_D[38] LA_D[37] LA_D[36] LA_D[35] LA_D[34] Ball No. D3 E3 D2 E2 A7 B7 A6 B6 C6 A5 B5 C5 A4 B4 C4 A3 B3 C3 B2 C2 C14 A13 B13 C13 A12 B12 C12 A11 B11 C11 Signal Name LA_D[19] LA_D[18] LA_D[17] LA_D[16] LA_D[15] LA_D[14] LA_D[13] LA_D[12] LA_D[11] LA_D[10] LA_D[9] LA_D[8] LA_D[7] LA_D[6] LA_D[5] LA_D[4] LA_D[3] LA_D[2] LA_D[1] LA_D[0] LA_A[20] LA_A[19] LA_A[18] LA_A[17] LA_A[16] LA_A[15] LA_A[14] LA_A[13] LA_A[12] LA_A[11] Ball No. A9 B9 F4 F5 G4 G5 H4 H5 J4 J5 K4 K5 L4 L5 M4 M5 N4 N5 G3 H1 H2 H3 J1 J2 J3 K1 K2 K3 L1 L2 Signal Name LA_OE0# LA_OE1# LB_D[63] LB_D[62] LB_D[61] LB_D[60] LB_D[59] LB_D[58] LB_D[57] LB_D[56] LB_D[55] LB_D[54] LB_D[53] LB_D[52] LB_D[51] LB_D[50] LB_D[49] LB_D[48] LB_D[47] LB_D[46] LB_D[45] LB_D[44] LB_D[43] LB_D[42] LB_D[41] LB_D[40] LB_D[39] LB_D[38] LB_D[37] LB_D[36] 98 Zarlink Semiconductor Inc. Data Sheet Ball No. A14 B14 D9 E9 D8 E8 D7 E7 D6 E6 D5 E5 D4 E4 AB4 AB5 AC4 AC5 AD4 AD5 W1 Y1 Y2 Y3 AA1 AA2 AA3 AB1 AB2 AB3 AC1 Signal Name LA_D[33] LA_D[32] LA_D[31] LA_D[30] LA_D[29] LA_D[28] LA_D[27] LA_D[26] LA_D[25] LA_D[24] LA_D[23] LA_D[22] LA_D[21] LA_D[20] LB_D[21] LB_D[20] LB_D[19] LB_D[18] LB_D[17] LB_D[16] LB_D[15] LB_D[14] LB_D[13] LB_D[12] LB_D[11] LB_D[10] LB_D[9] LB_D[8] LB_D[7] LB_D[6] LB_D[5] Ball No. D11 E11 A10 B10 D10 E10 A8 C7 B8 C1 C9 D12 E12 C8 U2 R28 P28 R29 AC29 AE28 AJ27 AF27 AJ25 AF24 AH23 AE19 AF21 AJ19 AF18 AJ17 AJ15 Signal Name LA_A[10] LA_A[9] LA_A[8] LA_A[7] LA_A[6] LA_A[5] LA_A[4] LA_A[3] LA_DSC# LA_CLK LA_WE# LA_WE0# LA_WE1# LA_OE# LB_OE1# MDC MDIO M_CLK NC NC NC NC NC NC NC NC M[15]_RXD[1] M[14]_RXD[1] M[13]_RXD[1] M[12]_RXD[1] M[11]_RXD[1] Ball No. L3 M1 M2 M3 U4 U5 V4 V5 W4 W5 Y4 Y5 AA4 AA5 AH7 AE6 AH5 AH2 AF2 AC27 AF29 AG27 AF26 AG25 AG23 AF23 AG21 AH21 AF19 AF17 AG17 ZL50417 Signal Name LB_D[35] LB_D[34] LB_D[33] LB_D[32] LB_D[31] LB_D[30] LB_D[29] LB_D[28] LB_D[27] LB_D[26] LB_D[25] LB_D[24] LB_D[23] LB_D[22] M[4]_RXD[0] M[3]_RXD[0] M[2]_RXD[0] M[1]_RXD[0] M[0]_RXD[0] NC NC NC NC NC NC NC NC M[15]_CRS_DV M[14]_CRS_DV M[13]_CRS_DV M[12]_CRS_DV Zarlink Semiconductor Inc. 99 ZL50417 Ball No. AC2 AC3 AD1 AD2 AD3 N3 N2 N1 P3 P2 P1 R5 R4 R3 R2 R1 T5 T4 T3 T2 T1 W3 W2 V1 G1 V3 P4 P5 V2 U1 AE8 Signal Name LB_D[4] LB_D[3] LB_D[2] LB_D[1] LB_D[0] LB_A[20] LB_A[19] LB_A[18] LB_A[17] LB_A[16] LB_A[15] LB_A[14] LB_A[13] LB_A[12] LB_A[11] LB_A[10] LB_A[9] LB_A[8] LB_A[7] LB_A[6] LB_A[5] LB_A[4] LB_A[3] LB_ADSC# LB_CLK LB_WE# LB_WE0# LB_WE1# LB_OE# LB_OE0# M[5]_TXEN Ball No. AF15 AJ13 AF12 AJ11 AJ9 AF9 AJ7 AF6 AJ5 AJ3 AF1 AC28 AF28 AH27 AE27 AH25 AE24 AF22 AF20 AE21 AH19 AH20 AH17 AH15 AE15 AH13 AE12 AH11 AH9 AE9 AH8 Signal Name M[10]_RXD[1] M[9]_RXD[1] M[8]_RXD[1] M[7]_RXD[1] M[6]_RXD[1] M[5]_RXD[1] M[4]_RXD[1] M[3]_RXD[1] M[2]_RXD[1] M[1]_RXD[1] M[0]_RXD[1] NC NC NC NC NC NC NC NC M[15]_RXD[0] M[14]_RXD[0] M[13]_RXD[0] M[12]_RXD[0] M[11]_RXD[0] M[10]_RXD[0] M[9]_RXD[0] M[8]_RXD[0] M[7]_RXD[0] M[6]_RXD[0] M[5]_RXD[0] M[6]_TXD[0] Ball No. AG15 AF14 AG13 AF11 AG11 AG9 AF8 AG7 AF5 AG5 AH3 AF3 AD29 AG28 AJ26 AE26 AJ24 AE23 AJ22 AJ20 AE20 AJ18 AJ21 AJ16 AJ14 AE14 AJ12 AE11 AJ10 AJ8 G27 Data Sheet Signal Name M[11]_CRS_DV M[10]_CRS_DV M[9]_CRS_DV M[8]_CRS_DV M[7]_CRS_DV M[6]_CRS_DV M[5]_CRS_DV M[4]_CRS_DV M[3]_CRS_DV M[2]_CRS_DV M[1]_CRS_DV M[0]_CRS_DV NC NC NC NC NC NC NC NC M[15]_TXEN M[14]_TXEN M[13]_TXEN M[12]_TXEN M[11]_TXEN M[10]_TXEN M[9]_TXEN M[8]_TXEN M[7]_TXEN M[6]_TXEN RESERVED 100 Zarlink Semiconductor Inc. Data Sheet Ball No. AJ6 AE5 AJ4 AG1 AE1 AD27 AH28 AG26 AE25 AG24 AE22 AJ23 AG20 AE18 AG18 AE16 AG16 AG14 AE13 AG12 AE10 AG10 AG8 AE7 AG6 AE4 AG4 AG3 AE3 AD28 AG29 Signal Name M[4]_TXEN M[3]_TXEN M[2]_TXEN M[1]_TXEN M[0]_TXEN NC NC NC NC NC NC NC NC M[15]_TXD[1] M[14]_TXD[1] M[13]_TXD[1] M[12]_TXD[1] M[11]_TXD[1] M[10]_TXD[1] M[9]_TXD[1] M[8]_TXD[1] M[7]_TXD[1] M[6]_TXD[1] M[5]_TXD[1] M[4]_TXD[1] M[3]_TXD[1] M[2]_TXD[1] M[1]_TXD[1] M[0]_TXD[1] NC NC Ball No. AF7 AH6 AF4 AH4 AG2 AE2 U26 U25 V26 V25 W26 W25 Y27 Y26 AA26 AA25 AB26 AB25 AC26 AC25 AD26 AD25 U27 V29 V28 V27 W29 W28 W27 Y29 Y28 Signal Name M[5]_TXD[0] M[4]_TXD[0] M[3]_TXD[0] M[2]_TXD[0] M[1]_TXD[0] M[0]_TXD[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M25_TXD[9] M25_TXD[8] M25_TXD[7] M25_TXD[6] M25_TXD[5] M25_TXD[4] M25_TXD[3] M25_TXD[2] M25_TXD[1] M25_TXD[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M25_RXD[9] M25_RXD[8] M25_RXD[7] Ball No. H29 H28 H27 J29 J28 J27 K29 K28 K27 L29 L28 L27 M29 M28 M27 G26 G25 H26 H25 J26 J25 K25 K26 M25 L26 M26 L25 N26 N25 P26 P25 ZL50417 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED M26_RXD[9] M26_RXD[8] M26_RXD[7] M26_RXD[6] M26_RXD[5] M26_RXD[4] M26_RXD[3] M26_RXD[2] M26_RXD[1] M26_RXD[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M26_TXD[9] M26_TXD[8] M26_TXD[7] M26_TXD[6] M26_TXD[5] M26_TXD[4] M26_TXD[3] M26_TXD[2] M26_TXD[1] M26_TXD[0] Zarlink Semiconductor Inc. 101 ZL50417 Ball No. AH26 AF25 AH24 AG22 AH22 AE17 AG19 AH18 AF16 AH16 AH14 AF13 AH12 AF10 AH10 B27 A27 E28 D28 C28 B28 E29 D29 C29 N29 P29 F3 E1 U3 C10 B24 NC NC NC NC NC NC M[15]_TXD[0] M[14]_TXD[0] M[13]_TXD[0] M[12]_TXD[0] M[11]_TXD[0] M[10]_TXD[0] M[9]_TXD[0] M[8]_TXD[0] M[7]_TXD[0] G2_LINK#/TSTOUT[8] G2_DPCOL#/TSTOUT[7] G2_RXTX#/TSTOUT[6] G1_LINK#/TSTOUT[5] G1_DPCOL#/TSTOUT[4] G1_RXTX#/TSTOUT[3] LED_BIT/TSTOUT[2] LED_SYN/TSTOUT[1] LED_CLK/TSTOUT[0] GREF_CLK1 GREF_CLK0 SCAN_EN SCLK T_MODE0 T_MODE1 TRUNK2 Signal Name Ball No. Y25 AA29 AA28 AA27 AB29 AB28 AB27 R26 T25 T26 T28 U28 R25 U29 T29 U18 V12 V13 V14 V15 V16 V17 V18 N14 N15 N16 N17 N18 P12 P13 P14 Signal Name M25_RXD[6] M25_RXD[5] M25_RXD[4] M25_RXD[3] M25_RXD[2] M25_RXD[1] M25_RXD[0] M25_TX_ER M25_TXCLK M25_TX_EN M25_RX_DV M25_RX_ER M25_CRS M25_COL M25_RXCLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. F28 G28 E25 G29 F29 F26 E26 F25 E24 D24 D25 D26 C26 D27 C27 N12 N13 K17 K18 M10 N10 M20 N20 U10 V10 U20 V20 Y12 Y13 Y17 Y18 Data Sheet Signal Name M26_RX_DV M26_RX_ER M26_CRS M26_COL M26_RXCLK M26_TX_EN M26_TX_ER M26_TXCLK BIST_DONE/TSTOUT[15] BIST_IN_PRC/TST0UT[14] MCT_ERR/TSTOUT[13] FCB_ERR/TSTOUT[12] CHECKSUM_OK/TSTOUT[11] INIT_START/TSTOUT[10] INIT_DONE/TSTOUT[9] VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 102 Zarlink Semiconductor Inc. Data Sheet Ball No. A21 C22 A26 B26 C25 A24 A25 F1 D1 D22 E23 E27 N28 N27 F2 G2 B22 A22 C23 B23 A23 C24 D23 T27 F27 C20 B20 A20 C21 E20 B25 RESIN# RESETOUT_ Reserved Reserved Reserved Reserved Reserved Reserved SCANCLK M25_MTXCLK M26_MTXCLK LA_CLK2 LA_CLK1 LA_CLK0 P_D RESERVED RESERVED Signal Name TRUNK1 TRUNK0 STROBE D0 AUTOFD SCL SDA AVCC AGND SCANCOL SCANLINK SCANMODE Ball No. P15 P16 C19 B19 A19 R13 R14 R15 R16 R17 R18 T12 T13 T14 T15 T16 T17 T18 U12 U13 U14 U15 U16 U17 M12 M13 M14 M15 P17 P18 R12 Signal Name VSS VSS OE_CLK2 OE_CLK1 OE_CLK0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. K12 K13 M16 M17 M18 F16 F17 N6 P6 R6 T6 U6 N24 P24 R24 T24 U24 AD13 AD14 AD15 AD16 AD17 F13 F14 F15 VDD VDD VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ZL50417 Signal Name Zarlink Semiconductor Inc. 103 ZL50417 14.4 14.4.1 AC/DC Timing Absolute Maximum Ratings Data Sheet Storage Temperature-65C to +150C Operating Temperature-40oC to + 85oC Supply Voltage VCC with Respect to VSS+3.0 V to +3.6 V Supply Voltage VDD with Respect to VSS+2.38 V to +2.75 V Voltage on Input Pins-0.5 V to (VCC + 3.3 V) Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 14.4.2 DC Electrical Characteristics VCC = 3.0 V to 3.6 V (3.3v +/- 10%)TAMBIENT = -40 C to +85 C VDD = 2.5V +10% - 5% 14.4.3 Recommended Operation Conditions Preliminary Symbol fosc IDD1 IDD2 VOH VOL VIH-TTL VIL-TTL IIH-5VT Parameter Description Min Frequency of Operation Supply Current - @ 100 MHz (VCC=3.3 V) Supply Current - @ 100 MHz (VDD =2.5 V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5V tolerant) Input Low Voltage (TTL 5V tolerant) Input Leakage Current (0.1 V < VIN < VDD2) (all pins except those with internal pull-up/pulldown resistors) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2m/s air flow VCC x 70% VCC - 0.5 0.5 VCC + 2.0 VCC x 30% 10 TypE 100 450 1500 Max Unit MHz mA mA V V V V A CIN COUT CI/O ja ja ja 5 5 7 11.2 10.2 8.9 pF pF pF C/W C/W C/W 104 Zarlink Semiconductor Inc. Data Sheet 14.5 14.5.1 Local Frame Buffer SBRAM Memory Interface Local SBRAM Memory Interface: LA_CLK L1 L2 ZL50417 LA_D[63:0] Figure 17 - Local Memory Interface - Input setup and hold timing LA_CLK L3-max L3-min LA_D[63:0] L4-max L4-min LA_A[20:3] L6-max L6-min LA_ADSC# L7-max L7-min LA_WE[1:0]# #### L8-max L8-min LA_OE[1:0]# L9-max L9-min LA_WE# L10-max L10-min LA_OE# Figure 18 - Local Memory Interface - Output valid delay timing Zarlink Semiconductor Inc. 105 ZL50417 AC Characteristics - Local frame buffer SBRAM Memory Interface -100MHz Symbol L1 L2 L3 L4 L6 L7 L8 L9 L10 Parameter Min (ns) LA_D[63:0] input set-up time LA_D[63:0] input hold time LA_D[63:0] output valid delay LA_A[20:3] output valid delay LA_ADSC# output valid delay LA_WE[1:0]#output valid delay LA_OE[1:0]# output valid delay LA_WE# output valid delay LA_OE# output valid delay 4 1.5 1.5 2 1 1 -1 1 1 7 7 7 7 1 7 5 Max (ns) Data Sheet Note: CL = 25pf CL = 30pf CL = 30pf CL = 25pf CL = 25pf CL = 25pf CL = 25pf 106 Zarlink Semiconductor Inc. Data Sheet 14.6 14.6.1 Local Switch Database SBRAM Memory Interface Local SBRAM Memory Interface LB_CLK L1 L2 ZL50417 LB_D[63:0] Figure 19 - Local Memory Interface - Input setup and hold timing LB_CLK L3-max L3-min LB_D[31:0] L4-max L4-min LB_A[21:2] L6-max L6-min LB_ADSC# L8-max L8-min LB_WE[1:0]# L9-max L9-min LB_OE[1:0]# L10-max L10-min LB_WE# L11-max L11-min LB_OE# Figure 20 - Local Memory Interface - Output valid delay timing AC Characteristics - Local Switch Database SBRAM Memory Interface -100MHz Symbol L1 L2 L3 L4 L6 L8 L9 L10 L11 Parameter LB_D[63:0] input set-up time LB_D[63:0] input hold time LB_D[63:0] output valid delay LB_A[20:3] output valid delay LB_ADSC# output valid delay LB_WE[1:0]#output valid delay LB_OE[1:0]# output valid delay LB_WE# output valid delay LB_OE# output valid delay Min (ns) 4 1.5 1.5 2 1 1 -1 1 1 7 7 7 7 1 7 5 CL = 25pf CL = 30pf CL = 30pf CL = 25pf CL = 25pf CL = 25pf CL = 25pf Max (ns) Note: Zarlink Semiconductor Inc. 107 ZL50417 14.7 14.7.1 AC Characteristics Reduced Media Independent Interface M_CLKI M6-max M6-min Data Sheet 15 M[23:0]_TXEN M7-max M7-min M[23:0] _TXD[1:0] 15 Figure 21 - AC Characteristics - Reduced media independent Interface M_CLKI M2 M[23:0]_RXD 15 M3 M[23:0]_CRS_DV 15 M4 M5 Figure 22 - AC Characteristics - Reduced Media Independent Interface AC Characteristics - Reduced Media Independent Interface -50MHz Symbol M2 M3 M4 M5 M6 M7 Parameter Min (ns) M[15:0]_RXD[1:0] Input Setup Time M[15:0]_RXD[1:0] Input Hold Time M[15:0]_CRS_DV Input Setup Time M[15:0]_CRS_DV Input Hold Time M[15:0]_TXEN Output Delay Time M[15:0]_TXD[1:0] Output Delay Time 4 1 4 1 2 2 11 11 CL = 20 pF CL = 20 pF Max (ns) Note: 108 Zarlink Semiconductor Inc. Data Sheet 14.7.2 Gigabit Media Independent Interface M25_TXCLK G12-max G12-min ZL50417 M25_TXD[7:0] [15:0] G13-max G13-min M25_TX_EN] G14-max G14-min M25_TX_ER Figure 23 - AC Characteristics- GMII M25_RXCLK G1 G2 G3 [7:0] M25_RXD[15:0] M25_RX_DV G5 G4 G6 M25_RX_ER G7 G8 M25_RX_CRS Figure 24 - AC Characteristics - Gigabit Media Independent Interface Zarlink Semiconductor Inc. 109 ZL50417 AC Characteristics - Gigabit Media Independent Interface -125Mhz Symbol G1 G2 G3 G4 G5 G6 G7 G8 G12 G13 G14 Parameter M[25]_RXD[7:0] Input Setup Times M[25]_RXD[7:0] Input Hold Times M[25]_RX_DV Input Setup Times M[25]_RX_DV Input Hold Times M[25]_RX_ER Input Setup Times M[25]_RX_ER Input Hold Times M[25]_CRS Input Setup Times M[25]_CRS Input Hold Times M[25]_TXD[7:0] Output Delay Times M[25]_TX_EN Output Delay Times M[25]_TX_ER Output Delay Times 2 1 2 1 2 1 2 1 1 1 1 6 6.5 6 Min (ns) Max (ns) Data Sheet Note: CL = 20pf CL = 20pf CL = 20pf M25_TXCLK TIMIN M25_TXD [9:0] TIMAX Figure 25 - Gigabit TBI Interface Transmit Timing M25_RXCLK M25_COL T2 T2 T3 T3 M25_RXD[9:0] Figure 26 - Gigabit TBI Interface Receive Timing Symbol T1 Parameter M25_TXD[9:0] Output Delay Time 1 Min (ns) Max (ns) 6 Note: CL = 20pf Table 12 - Output Delay Timing 110 Zarlink Semiconductor Inc. Data Sheet Symbol T2 T3 Parameter M25_RXD[9:0] Input Setup Time M25_RXD[9:0] Input Hold Time 3 3 Min (ns) Max (ns) ZL50417 Note: Table 13 - Input Setup Timing M26_TXCLK G12-max G12-min M26_TXD [7:0] [15:0] G13-max G13-min M26_TX_EN] G14-max G14-min M26_TX_ER Figure 27 - AC Characteristics- GMII M26_RXCLK G1 G2 M26_RXD[15:0] [7:0] G3 G4 M26_RX_DV G5 G6 M26_RX_ER G7 G8 M26_RX_CRS Figure 28 - AC Characteristics - Gigabit Media Independent Interface AC Characteristics - Gigabit Media Independent Interface -125Mhz Symbol G1 G2 Parameter Min (ns) M[26]_RXD[7:0] Input Setup Times M[26]_RXD[7:0] Input Hold Times 2 1 Max (ns) Note: Zarlink Semiconductor Inc. 111 ZL50417 AC Characteristics - Gigabit Media Independent Interface G3 G4 G5 G6 G7 G8 G12 G13 G14 M[26]_RX_DV Input Setup Times M[26]_RX_DV Input Hold Times M[26]_RX_ER Input Setup Times M[26]_RX_ER Input Hold Times M[26]_CRS Input Setup Times M[26]_CRS Input Hold Times M[26]_TXD[7:0] Output Delay Times M[26]_TX_EN Output Delay Times M[26]_TX_ER Output Delay Times 2 1 2 1 2 1 1 1 1 6 6.5 6 Data Sheet CL = 20pf CL = 20pf CL = 20pf M26_TXCLK TIMIN M26_TXD [9:0] TIMAX Figure 29 - Gigabit TBI Interface Transmit Timing M26_RXCLK M26_COL T2 T2 T3 T3 M26_RXD[9:0] Figure 30 - Gigabit TBI Interface Timing Symbol T1 Parameter M26_TXD[9:0] Output Delay Time 1 Min (ns) Max (ns) 6 Note: CL = 20pf Table 14 - Output Delay Timing 112 Zarlink Semiconductor Inc. Data Sheet Symbol T2 T3 Parameter M26_RXD[9:0] Input Setup Time M26_RXD[9:0] Input Hold Time 3 3 Min (ns) Max (ns) ZL50417 Note: Table 15 - Input Setup Timing 14.7.3 LED Interface LED_CLK LE5-max LE5-min LED_SYN LE6-max LE6-min LED_BIT Figure 31 - AC Characteristics - LED Interface Variable FREQ. Symbol LE5 LE6 Parameter Min (ns) LED_SYN Output Valid Delay LED_BIT Output Valid Delay -1 -1 Max (ns) 7 7 CL = 30pf CL = 30pf Note: Table 17- AC Characteristics - LED Interface Zarlink Semiconductor Inc. 113 ZL50417 14.7.4 SCANLINK SCANCOL Output Delay Timing Data Sheet SCANCLK C5-max C5-min SCANLINK C7-max C7-min SCANCOL Figure 32 - SCANLINK SCANCOL Output Delay Timing SCANCLK C1 C2 SCANLINK C3 C4 SCANCOL Figure 33 - SCANLINK, SCANCOL Setup Timing -25MHz Symbol C1 C2 C3 C4 C5 C7 Parameter Min (ns) SCANLINK input set-up time SCANLINK input hold time SCANCOL input setup time SCANCOL input hold time SCANLINK output valid delay SCANCOL output valid delay 20 2 20 1 0 0 10 10 CL = 30pf CL = 30pf Max (ns) Note: Table 16 - SCANLINK, SCANCOL Timing 114 Zarlink Semiconductor Inc. Data Sheet 14.7.5 MDIO Input Setup and Hold Timing MDC D1 D2 ZL50417 MDIO Figure 34 - MDIO Input Setup and Hold Timing MDC D3-max D3-min MDIO Figure 35 - MDIO Output Delay Timing 1MHz Symbol D1 D2 D3 Parameter Min (ns) MDIO input setup time MDIO input hold time MDIO output delay time 10 2 1 Table 17 - MDIO Timing 20 CL = 50pf Max (ns) Note: Zarlink Semiconductor Inc. 115 ZL50417 14.7.6 IC Input Setup Timing SCL S1 S2 Data Sheet SDA Figure 36 - IC Input Setup Timing SCL S3-max S3-min SDA Figure 37 - IC Output Delay Timing 50KHz Symbol S1 S2 S3* Parameter Min (ns) SDA input setup time SDA input hold time SDA output delay time 20 1 4 usec 6 usec CL = 30pf Max (ns) Note: * Open Drain Output. Low to High transistor is controlled by external pullup resistor. Table 18 - IC Timing 116 Zarlink Semiconductor Inc. Data Sheet 14.7.7 Serial Interface Setup Timing ZL50417 STROBE D1 D2 D4 D1 D2 D5 D0 Figure 38 - Serial Interface Setup Timing STROBE D3-max D3-min AutoFd Figure 39 - Serial Interface Output Delay Timing Symbol D1 D2 D3 D4 D5 D0 setup time D0 hold time Parameter Min (ns) 20 3s 1 5s 5s Max (ns) Note: AutoFd output delay time Strobe low time Strobe high time 50 CL = 100pf Table 19 - Serial Interface Timing Zarlink Semiconductor Inc. 117 E1 E DIMENSION A A1 A2 D D1 E E1 b e MIN MAX 2.20 2.46 0.50 0.70 1.17 REF 37.70 37.30 34.50 REF 37.70 37.30 34.50 REF 0.60 0.90 1.27 553 Conforms to JEDEC MS - 034 e D D1 A2 b NOTE: 1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM Package Code ISSUE ACN DATE APPRD. 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